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公开(公告)号:US07437401B2
公开(公告)日:2008-10-14
申请号:US10783820
申请日:2004-02-20
申请人: Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Gregory Starr , William Hwang , Kumara Tharmalingam
发明人: Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Gregory Starr , William Hwang , Kumara Tharmalingam
IPC分类号: G06F7/48
CPC分类号: G06F7/5443 , H03K19/17732
摘要: A programmable logic device is provided that includes a MAC block having mode splitting capabilities. Different modes of operation may be implemented simultaneously whereby the multipliers and other DSP circuitry of the MAC block may be allocated among the different modes of operation. For example, one multiplier may be used to implement a multiply mode while another two multipliers may be used to implement a sum of two multipliers mode.
摘要翻译: 提供了一种可编程逻辑器件,其包括具有模式分离能力的MAC块。 可以同时实现不同的操作模式,从而可以在不同的操作模式之间分配MAC块的乘法器和其它DSP电路。 例如,可以使用一个乘法器来实现乘法模式,而另外两个乘法器可以用于实现两个乘法器模式的和。
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公开(公告)号:US20050187998A1
公开(公告)日:2005-08-25
申请号:US10783820
申请日:2004-02-20
申请人: Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Gregory Starr , William Hwang , Kumara Tharmalingam
发明人: Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Gregory Starr , William Hwang , Kumara Tharmalingam
IPC分类号: G06F7/544 , G06F15/00 , H03K19/177
CPC分类号: G06F7/5443 , H03K19/17732
摘要: A programmable logic device is provided that includes a MAC block having mode splitting capabilities. Different modes of operation may be implemented simultaneously whereby the multipliers and other DSP circuitry of the MAC block may be allocated among the different modes of operation. For example, one multiplier may be used to implement a multiply mode while another two multipliers may be used to implement a sum of two multipliers mode.
摘要翻译: 提供了一种可编程逻辑器件,其包括具有模式分离能力的MAC块。 可以同时实现不同的操作模式,从而可以在不同的操作模式之间分配MAC块的乘法器和其它DSP电路。 例如,可以使用一个乘法器来实现乘法模式,而另外两个乘法器可以用于实现两个乘法器模式的和。
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公开(公告)号:US20050187999A1
公开(公告)日:2005-08-25
申请号:US10783829
申请日:2004-02-20
申请人: Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人: Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
CPC分类号: G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要: Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译: 饱和度和舍入能力在MAC块中实现,以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累加电路。 这些功能支持任何合适的价值表示形式,包括x.15格式。 乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。
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公开(公告)号:US20090100122A1
公开(公告)日:2009-04-16
申请号:US12324055
申请日:2008-11-26
申请人: Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人: Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号: G06F7/38
CPC分类号: G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要: Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译: 饱和度和舍入能力在MAC模块中实现,以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累积电路。 这些功能支持任何合适的价值表示形式,包括x.15格式。 乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。
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公开(公告)号:US08615543B1
公开(公告)日:2013-12-24
申请号:US13166119
申请日:2011-06-22
申请人: Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人: Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号: G06F7/38
CPC分类号: G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要: Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译: 饱和度和舍入能力在MAC块中实现,以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累加电路。 这些功能支持任何合适的价值表示形式,包括x.15格式。 乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。
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公开(公告)号:US07467176B2
公开(公告)日:2008-12-16
申请号:US10783829
申请日:2004-02-20
申请人: Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人: Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号: G06F7/38
CPC分类号: G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要: Saturation and rounding capabilities are implemented in multiply-accumulate (MAC) blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译: 饱和度和舍入能力在乘法累加(MAC)块中实现,以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累加电路。 这些功能支持任何合适的价值表示形式,包括x.15格式。 乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。
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公开(公告)号:US4709215A
公开(公告)日:1987-11-24
申请号:US814546
申请日:1985-12-30
摘要: A method and apparatus are disclosed for regulating the operation of a TWT. The TWT regulation is achieved by detecting the operating condition of the TWT, e.g., by measuring dynamic gain, and regulating feedback of the TWT output in response to the TWT operating condition. The invention is preferably implemented so as to augment the TWT input drive from an exciter source to induce the TWT to drive itself into saturation. The inventive technique comprises determining whether the TWT is operating in a desired operating condition, e.g., saturation, feeding back to the TWT input a portion of the TWT output power to the TWT input, and regulating the feedback signal to keep the TWT operating in the desired condition. Determination of whether the TWT is operating in a saturation condition may be affected through measurement of the TWT dynamic gain. The invention permits dynamic management of the feedback to accommodate variations in gain of the TWT, e.g., such as those during TWT input pulse rise and pulse fall times. The invention maintains the TWT in the desired condition despite changes in the condition of the TWT or in the signals applied to the TWT.
摘要翻译: 公开了一种用于调节TWT的操作的方法和装置。 通过检测TWT的操作条件,例如通过测量动态增益,以及响应于TWT操作条件调节TWT输出的反馈来实现TWT调节。 优选实施本发明,以便从激励器源增加TWT输入驱动以引起TWT驱动自身进入饱和。 本发明的技术包括确定TWT是否在期望的操作条件下工作,例如饱和,向TWT输入TWT输入的一部分TWT输出功率到TWT输入,以及调节反馈信号以保持TWT在 所需条件。 确定TWT是否工作在饱和状态可能会受到TWT动态增益的测量的影响。 本发明允许动态管理反馈以适应TWT的增益变化,例如在TWT输入脉冲上升和脉冲下降时间期间的增益变化。 本发明将TWT保持在期望的状态,尽管TWT的状况或施加于TWT的信号发生变化。
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