公开(公告)号：US20060085662A1

公开(公告)日：2006-04-20

申请号：US11292844

申请日：2005-12-01

申请人： Lew Chua-Eoan ,  Atsushi Hasegawa ,  Hsuan-Wen Wang

发明人： Lew Chua-Eoan ,  Atsushi Hasegawa ,  Hsuan-Wen Wang

IPC分类号： G06F1/04

CPC分类号： G06F5/06 ,  G06F1/06

摘要： An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals, and a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit. An interface circuit according to one embodiment of the invention can be used advantageously for controlling the flow of data between a CPU and an external memory.

摘要翻译： 根据本发明的一个实施例的接口电路包括时钟信号，耦合到时钟信号线并产生参考时钟信号的第一锁相环，接收参考时钟信号的第二锁相环， 产生一个或多个相移参考时钟信号，以及数据收发器电路，其耦合以接收所述时钟信号，所述参考时钟信号或所述相移基准时钟信号中的至少一个，以控制所述相移参考时钟信号之间的数据流 第一电路和第二电路。 根据本发明的一个实施例的接口电路可以有利地用于控制CPU和外部存储器之间的数据流。

公开(公告)号：US07003686B2

公开(公告)日：2006-02-21

申请号：US10152653

申请日：2002-05-20

申请人： Lew Chua-Eoan ,  Atsushi Hasegawa ,  Hsuan-Wen Wang

发明人： Lew Chua-Eoan ,  Atsushi Hasegawa ,  Hsuan-Wen Wang

IPC分类号： G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F1/12

CPC分类号： G06F5/06 ,  G06F1/06

摘要： An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals, and a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit. An interface circuit according to one embodiment of the invention can be used advantageously for controlling the flow of data between a CPU and an external memory.

公开(公告)号：US07181639B2

公开(公告)日：2007-02-20

申请号：US11292844

申请日：2005-12-01

申请人： Lew Chua-Eoan ,  Atsushi Hasegawa ,  Hsuan-Wen Wang

发明人： Lew Chua-Eoan ,  Atsushi Hasegawa ,  Hsuan-Wen Wang

IPC分类号： G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F1/12

CPC分类号： G06F5/06 ,  G06F1/06

摘要： An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals, and a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit. An interface circuit according to one embodiment of the invention can be used advantageously for controlling the flow of data between a CPU and an external memory.

摘要翻译： 根据本发明的一个实施例的接口电路包括时钟信号，耦合到时钟信号线并产生参考时钟信号的第一锁相环，接收参考时钟信号的第二锁相环， 产生一个或多个相移参考时钟信号，以及数据收发器电路，其耦合以接收所述时钟信号，所述参考时钟信号或所述相移基准时钟信号中的至少一个，以控制所述相移参考时钟信号之间的数据流 第一电路和第二电路。 根据本发明的一个实施例的接口电路可以有利地用于控制CPU和外部存储器之间的数据流。

公开(公告)号：US20050013251A1

公开(公告)日：2005-01-20

申请号：US10622806

申请日：2003-07-18

申请人： Hsuan-Wen Wang ,  Jaisimha Bannur ,  Anujan Varma

发明人： Hsuan-Wen Wang ,  Jaisimha Bannur ,  Anujan Varma

IPC分类号： H04L12/26 ,  H04L12/56

CPC分类号： H04L47/2458 ,  H04L47/10 ,  H04L47/17 ,  H04L47/2441 ,  H04L47/263 ,  H04L47/323 ,  H04L49/252 ,  H04L49/3045

摘要： In general, in one aspect, the disclosure describes a flow control hub that includes a scoreboard memory device to maintain flow control status for a plurality of flows. Each of the flows is identified by an associated index. The apparatus also includes an address decoder to receive a flow control message and to determine an associated index based on the address portion. The apparatus further includes an updater to update the flow control status in said memory device based on the received flow control message.

摘要翻译： 通常，在一个方面，本公开描述了一种流控制中心，其包括记分板存储装置，以维持多个流的流量控制状态。 每个流都由相关联的索引来标识。 该装置还包括地址解码器，用于接收流控制消息并且基于地址部分确定相关索引。 该装置还包括更新器，用于基于所接收的流控制消息来更新所述存储设备中的流控制状态。

公开(公告)号：US06496905B1

公开(公告)日：2002-12-17

申请号：US09410555

申请日：1999-10-01

申请人： Shinichi Yoshioka ,  Hsuan-Wen Wang ,  Rajesh Chopra ,  Jun-Wen Tsong

发明人： Shinichi Yoshioka ,  Hsuan-Wen Wang ,  Rajesh Chopra ,  Jun-Wen Tsong

IPC分类号： G06F1200

CPC分类号： G06F12/0879

摘要： Methods and an apparatus for buffering write operations are disclosed. In one embodiment, a processing system bursts data to a bus. The processing system includes a memory cache, a write buffer unit, and a control unit. The memory cache produces an address and data. Included in the write buffer unit are a plurality of data locations coupled to the memory cache. The control unit directs the first data to any of the plurality of data locations.

摘要翻译： 公开了用于缓冲​​写入操作的方法和装置。 在一个实施例中，处理系统将数据突发到总线。 处理系统包括存储器高速缓存，写入缓冲器单元和控制单元。 内存缓存生成一个地址和数据。 包括在写入缓冲器单元中的是耦合到存储器高速缓存的多个数据位置。 控制单元将第一数据引导到多个数据位置中的任一个。