公开(公告)号：US06803805B2

公开(公告)日：2004-10-12

申请号：US10118753

申请日：2002-04-09

申请人： Li-Kong Wang ,  Louis L. Hsu ,  Fanchieh Yee

发明人： Li-Kong Wang ,  Louis L. Hsu ,  Fanchieh Yee

IPC分类号： G05F302

CPC分类号： G06F1/26 ,  Y10T307/25

摘要： A system on a chip (SOC voltage generator) system is provided for supplying at least one voltage level to a plurality of units on a chip having an SOC design. The system includes a plurality of local DC voltage generators distributed throughout the chip, each local DC voltage generator independently supplying voltage to at least one unit of the plurality of units, each local DC voltage generator including a regulator system outputting one pump control signal; and a pump system receiving the one pump control signal and outputting at least one voltage level in accordance with the one pump control signal. Furthermore a method for supplying voltage to a plurality of units on a chip having an SOC design is provided. The method includes the steps of distributing a plurality of local DC voltage generators throughout the chip; and supplying at least one voltage level to the plurality of units via the plurality of local DC voltage generators.

摘要翻译： 提供了一种芯片系统（SOC电压发生器）系统，用于向具有SOC设计的芯片上的多个单元提供至少一个电压电平。 该系统包括分布在整个芯片上的多个本地直流电压发生器，每个局部直流电压发生器独立地向多个单元中的至少一个单元提供电压，每个局部直流电压发生器包括输出一个泵控制信号的调节器系统; 以及泵系统，接收所述一个泵控制信号，并根据所述一个泵控制信号输出至少一个电压电平。 此外，提供了一种用于向具有SOC设计的芯片上的多个单元提供电压的方法。 该方法包括在整个芯片上分配多个局部DC电压发生器的步骤; 并且经由所述多个本地DC电压发生器向所述多个单元提供至少一个电压电平。

公开(公告)号：US08020120B2

公开(公告)日：2011-09-13

申请号：US11865252

申请日：2007-10-01

申请人： Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Thomas Ludwig ,  Rama Nand Sing ,  Fanchieh Yee

发明人： Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Thomas Ludwig ,  Rama Nand Sing ,  Fanchieh Yee

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method for layout design includes steps or acts of: receiving a layout for design of an integrated circuit chip; designing mask shapes for the layout; transmitting the mask shapes to a litho simulator for generating wafer shapes; receiving the wafer shapes; calculating electrically equivalent gate lengths for the wafer shapes; analyzing the gate lengths to check for conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate lengths; placing markers on the layout at those locations where the gate length violates the threshold value; and generating a histogram of gate lengths for comparing layouts for electrically equivalent gate lengths for layout quality.

摘要翻译： 一种用于布局设计的方法包括以下步骤或动作：接收用于集成电路芯片设计的布局; 设计布局的面具形状; 将掩模形状传送到用于产生晶片形状的光刻模拟器; 接收晶片形状; 计算晶片形状的等效栅极长度; 分析所述栅极长度以检查与阈值的一致性，其中所述阈值表示电等效栅极长度的期望值; 在栅极长度违反阈值的位置放置标记在布局上; 以及生成用于比较用于布局质量的电等效栅极长度的布局的栅极长度的直方图。

公开(公告)号：US20090089726A1

公开(公告)日：2009-04-02

申请号：US11865252

申请日：2007-10-01

申请人： Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Thomas Ludwig ,  Rama Nand Singh ,  Fanchieh Yee

发明人： Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Thomas Ludwig ,  Rama Nand Singh ,  Fanchieh Yee

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method for layout design includes steps or acts of: receiving a layout for design of an integrated circuit chip; designing mask shapes for the layout; transmitting the mask shapes to a litho simulator for generating wafer shapes; receiving the wafer shapes; calculating electrically equivalent gate lengths for the wafer shapes; analyzing the gate lengths to check for conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate lengths; placing markers on the layout at those locations where the gate length violates the threshold value; and generating a histogram of gate lengths for comparing layouts for electrically equivalent gate lengths for layout quality.

摘要翻译： 一种用于布局设计的方法包括以下步骤或动作：接收用于集成电路芯片设计的布局; 设计布局的面具形状; 将掩模形状传送到用于产生晶片形状的光刻模拟器; 接收晶片形状; 计算晶片形状的等效栅极长度; 分析所述栅极长度以检查与阈值的一致性，其中所述阈值表示电等效栅极长度的期望值; 在栅极长度违反阈值的位置放置标记在布局上; 以及生成用于比较用于布局质量的电等效栅极长度的布局的栅极长度的直方图。