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    Layout quality gauge for integrated circuit design
    1.
    发明授权
    Layout quality gauge for integrated circuit design 有权
    集成电路设计的布局质量计

    公开(公告)号：US08020120B2

    公开(公告)日：2011-09-13

    申请号：US11865252

    申请日：2007-10-01

    申请人： Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Thomas Ludwig ,  Rama Nand Sing ,  Fanchieh Yee

    发明人： Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Thomas Ludwig ,  Rama Nand Sing ,  Fanchieh Yee

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method for layout design includes steps or acts of: receiving a layout for design of an integrated circuit chip; designing mask shapes for the layout; transmitting the mask shapes to a litho simulator for generating wafer shapes; receiving the wafer shapes; calculating electrically equivalent gate lengths for the wafer shapes; analyzing the gate lengths to check for conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate lengths; placing markers on the layout at those locations where the gate length violates the threshold value; and generating a histogram of gate lengths for comparing layouts for electrically equivalent gate lengths for layout quality.

    摘要翻译： 一种用于布局设计的方法包括以下步骤或动作：接收用于集成电路芯片设计的布局; 设计布局的面具形状; 将掩模形状传送到用于产生晶片形状的光刻模拟器; 接收晶片形状; 计算晶片形状的等效栅极长度; 分析所述栅极长度以检查与阈值的一致性，其中所述阈值表示电等效栅极长度的期望值; 在栅极长度违反阈值的位置放置标记在布局上; 以及生成用于比较用于布局质量的电等效栅极长度的布局的栅极长度的直方图。

    Layout Quality Gauge for Integrated Circuit Design
    2.
    发明申请
    Layout Quality Gauge for Integrated Circuit Design 有权
    集成电路设计布局质量计

    公开(公告)号：US20090089726A1

    公开(公告)日：2009-04-02

    申请号：US11865252

    申请日：2007-10-01

    申请人： Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Thomas Ludwig ,  Rama Nand Singh ,  Fanchieh Yee

    发明人： Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Thomas Ludwig ,  Rama Nand Singh ,  Fanchieh Yee

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method for layout design includes steps or acts of: receiving a layout for design of an integrated circuit chip; designing mask shapes for the layout; transmitting the mask shapes to a litho simulator for generating wafer shapes; receiving the wafer shapes; calculating electrically equivalent gate lengths for the wafer shapes; analyzing the gate lengths to check for conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate lengths; placing markers on the layout at those locations where the gate length violates the threshold value; and generating a histogram of gate lengths for comparing layouts for electrically equivalent gate lengths for layout quality.

    摘要翻译： 一种用于布局设计的方法包括以下步骤或动作：接收用于集成电路芯片设计的布局; 设计布局的面具形状; 将掩模形状传送到用于产生晶片形状的光刻模拟器; 接收晶片形状; 计算晶片形状的等效栅极长度; 分析所述栅极长度以检查与阈值的一致性，其中所述阈值表示电等效栅极长度的期望值; 在栅极长度违反阈值的位置放置标记在布局上; 以及生成用于比较用于布局质量的电等效栅极长度的布局的栅极长度的直方图。

    CA resistance variability prediction methodology
    4.
    发明授权
    CA resistance variability prediction methodology 有权
    CA抗性变异性预测方法

    公开(公告)号：US07831941B2

    公开(公告)日：2010-11-09

    申请号：US11968458

    申请日：2008-01-02

    申请人： Dureseti Chidambarrao ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Rama N. Singh ,  Roger Y. Tsai

    发明人： Dureseti Chidambarrao ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Rama N. Singh ,  Roger Y. Tsai

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A methodology for obtaining improved prediction of CA resistance in electronic circuits and, particularly, an improved CA resistance model adapted to capture larger than anticipated “out of spec” regime. In one embodiment, a novel bucketization scheme is implemented that is codified to provide a circuit designer with considerably better design options for handling large CA variability as seen through the design manual. The tools developed for modeling the impact of CA variable resistance phenomena provide developers with a resistance model, such as conventionally known, modified with a new CA model Basis including a novel CA intrinsic resistance model, and, a novel CA layout bucketization model.

    摘要翻译： 一种用于获得电子电路中CA电阻改进预测的方法，特别是改进的CA电阻模型，适用于捕获大于预期的“超出规范”状态。 在一个实施例中，实现了一种新颖的分层方案，其编码为电路设计者提供了相当好的设计选项，用于处理大的CA变异性，如通过设计手册所看到的。 开发用于建模CA可变电阻现象影响的工具为开发人员提供了一种电阻模型，如常规已知的，使用新的CA模型Basis进行修改，包括新颖的CA内在电阻模型，以及新颖的CA布局分层模型。

    Lithographic process window optimization under complex constraints on edge placement
    6.
    发明授权
    Lithographic process window optimization under complex constraints on edge placement 有权
    边缘放置复杂约束下的平版印刷工艺窗口优化

    公开(公告)号：US07269817B2

    公开(公告)日：2007-09-11

    申请号：US10776901

    申请日：2004-02-10

    申请人： Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Daniel L. Ostapko ,  Alan E. Rosenbluth ,  Nakgeuon Seong

    发明人： Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Daniel L. Ostapko ,  Alan E. Rosenbluth ,  Nakgeuon Seong

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A method and system for layout optimization relative to lithographic process windows which facilitates lithographic constraints to be non-localized in order to impart a capability of printing a given circuit with a process window beyond the process windows which are attainable with conventional simplified design rules. Pursuant to the method and system, lithographic capability and process windows are maximized to satisfy local circuit requirements and in order to achieve a maximally efficient layout. In this connection, there is employed a method utilizing a generalized lithographic process window as a measure when layout optimization is extended to a degree beyond that achieved by the simple fixed design rules which are applied to the design rules obtained is the advantage that a lithographic process window is determined purely through the calculation of image intensities and slopes, and as a result, the method can be quite rapid in application because it is possible to take advantage of known methods for rapid calculation of image intensity, and because there is obviated the need for geometrical shape processing during optimization.

    摘要翻译： 一种用于相对于光刻工艺窗口的布局优化的方法和系统，其有助于光刻约束被非局部化，以便赋予给定电路打印超过可以​​用常规简化设计规则达到的过程窗口的处理窗口的能力。 根据方法和系统，光刻能力和工艺窗口最大化，以满足局部电路要求，并实现最大限度的高效布局。 在这方面，采用一种利用广义平版印刷工艺窗口作为测量的方法，当布局优化扩展到超过通过简单的固定设计规则实现的程度时，应用于所获得的设计规则是光刻工艺的优点 通过计算图像强度和斜率来确定窗口，结果，该方法在应用中可以相当快速，因为可以利用已知的方法来快速计算图像强度，并且因为不需要 用于优化期间的几何形状处理。

    CA RESISTANCE VARIABILITY PREDICTION METHODOLOGY
    8.
    发明申请
    CA RESISTANCE VARIABILITY PREDICTION METHODOLOGY 有权
    CA抗性变异性预测方法

    公开(公告)号：US20090171644A1

    公开(公告)日：2009-07-02

    申请号：US11968458

    申请日：2008-01-02

    申请人： Dureseti Chidambarrao ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Rama N. Singh ,  Roger Y. Tsai

    发明人： Dureseti Chidambarrao ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin-Fuw Lee ,  Rama N. Singh ,  Roger Y. Tsai

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A methodology for obtaining improved prediction of CA resistance in electronic circuits and, particularly, an improved CA resistance model adapted to capture larger than anticipated “out of spec” regime. In one embodiment, a novel bucketization scheme is implemented that is codified to provide a circuit designer with considerably better design options for handling large CA variability as seen through the design manual. The tools developed for modeling the impact of CA variable resistance phenomena provide developers with a resistance model, such as conventionally known, modified with a new CA model Basis including a novel CA intrinsic resistance model, and, a novel CA layout bucketization model.

    摘要翻译： 一种用于获得电子电路中CA电阻改进预测的方法，特别是改进的CA电阻模型，适用于捕获大于预期的“超出规范”状态。 在一个实施例中，实现了一种新颖的分层方案，其编码为电路设计者提供了相当好的设计选项，用于处理大的CA变异性，如通过设计手册所看到的。 开发用于建模CA可变电阻现象影响的工具为开发人员提供了一种电阻模型，如常规已知的，使用新的CA模型Basis进行修改，包括新颖的CA内在电阻模型，以及新颖的CA布局分层模型。