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309 条记录 (耗时 0.029 秒)

    Distributed DC voltage generator for system on chip
    1.
    发明授权
    Distributed DC voltage generator for system on chip 失效
    分布式直流电压发生器，用于片上系统

    公开(公告)号：US06803805B2

    公开(公告)日：2004-10-12

    申请号：US10118753

    申请日：2002-04-09

    申请人： Li-Kong Wang ,  Louis L. Hsu ,  Fanchieh Yee

    发明人： Li-Kong Wang ,  Louis L. Hsu ,  Fanchieh Yee

    IPC分类号： G05F302

    CPC分类号： G06F1/26 ,  Y10T307/25

    摘要： A system on a chip (SOC voltage generator) system is provided for supplying at least one voltage level to a plurality of units on a chip having an SOC design. The system includes a plurality of local DC voltage generators distributed throughout the chip, each local DC voltage generator independently supplying voltage to at least one unit of the plurality of units, each local DC voltage generator including a regulator system outputting one pump control signal; and a pump system receiving the one pump control signal and outputting at least one voltage level in accordance with the one pump control signal. Furthermore a method for supplying voltage to a plurality of units on a chip having an SOC design is provided. The method includes the steps of distributing a plurality of local DC voltage generators throughout the chip; and supplying at least one voltage level to the plurality of units via the plurality of local DC voltage generators.

    摘要翻译： 提供了一种芯片系统（SOC电压发生器）系统，用于向具有SOC设计的芯片上的多个单元提供至少一个电压电平。 该系统包括分布在整个芯片上的多个本地直流电压发生器，每个局部直流电压发生器独立地向多个单元中的至少一个单元提供电压，每个局部直流电压发生器包括输出一个泵控制信号的调节器系统; 以及泵系统，接收所述一个泵控制信号，并根据所述一个泵控制信号输出至少一个电压电平。 此外，提供了一种用于向具有SOC设计的芯片上的多个单元提供电压的方法。 该方法包括在整个芯片上分配多个局部DC电压发生器的步骤; 并且经由所述多个本地DC电压发生器向所述多个单元提供至少一个电压电平。

    Method and structure for providing improved thermal conduction for silicon semiconductor devices
    2.
    发明授权
    Method and structure for providing improved thermal conduction for silicon semiconductor devices 失效

    公开(公告)号：US07052937B2

    公开(公告)日：2006-05-30

    申请号：US10429758

    申请日：2003-05-05

    申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsorng-Dih Yuan

    发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsorng-Dih Yuan

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L23/3677 ,  H01L23/3732 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure. Yet another embodiment comprises diamond sidewalls formed along the device walls in thermal contact with the device junctions to provide heat dissipation through the device junctions to underlying cooling structures. It is also proposed that the foregoing structures, and combinations of the foregoing structures, could be used in conjunction with other known cooling schemes.

    Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
    4.
    发明授权
    Method of fabricating silicon devices on sapphire with wafer bonding at low temperature 失效
    在低温下用蓝宝石制造硅器件的方法

    公开(公告)号：US06911375B2

    公开(公告)日：2005-06-28

    申请号：US10452715

    申请日：2003-06-02

    申请人： Kathryn W. Guarini ,  Louis L. Hsu ,  Leathen Shi ,  Dinkar V. Singh ,  Li-Kong Wang

    发明人： Kathryn W. Guarini ,  Louis L. Hsu ,  Leathen Shi ,  Dinkar V. Singh ,  Li-Kong Wang

    IPC分类号： H01L21/30 ,  H01L21/68 ,  H01L21/762

    CPC分类号： H01L21/76256 ,  H01L21/6835 ,  H01L21/76254 ,  H01L2221/68368 ,  H01L2924/19041

    摘要： Described is a method for making silicon on sapphire structures, and devices therefrom. The inventive method of forming integrated circuits on a sapphire substrate comprises the steps of providing a device layer on an oxide layer of a temporary substrate; bonding the device layer to a handling substrate; removing the temporary substrate to provide a structure containing the device layer between the oxide layer and the handling substrate; bonding a sapphire substrate to the oxide layer; removing the handling substrate from the structure; and annealing the final structure to provide a substrate comprising the oxide layer between the device layer and the sapphire substrate. The sapphire substrate may comprise bulk sapphire or may be a conventional substrate material with an uppermost sapphire layer.

    摘要翻译： 描述了在蓝宝石结构上制造硅的方法及其装置。 在蓝宝石衬底上形成集成电路的本发明的方法包括以下步骤：在临时衬底的氧化物层上提供器件层; 将所述器件层接合到处理衬底; 去除所述临时衬底以提供在所述氧化物层和所述处理衬底之间包含所述器件层的结构; 将蓝宝石衬底结合到氧化物层; 从结构中去除处理基板; 并退火最终结构以提供包括在器件层和蓝宝石衬底之间的氧化物层的衬底。 蓝宝石衬底可以包括散装蓝宝石，或者可以是具有最上层蓝宝石层的常规衬底材料。

    Method and apparatus for performing data access and refresh operations in different sub-arrays of a DRAM cache memory
    6.
    发明授权
    Method and apparatus for performing data access and refresh operations in different sub-arrays of a DRAM cache memory 有权
    用于在DRAM高速缓冲存储器的不同子阵列中执行数据访问和刷新操作的方法和装置

    公开(公告)号：US06697909B1

    公开(公告)日：2004-02-24

    申请号：US09660431

    申请日：2000-09-12

    申请人： Li-Kong Wang ,  Louis L. Hsu

    发明人： Li-Kong Wang ,  Louis L. Hsu

    IPC分类号： G06F1300

    CPC分类号： G11C11/40603 ,  G06F12/0802 ,  G11C11/406 ,  G11C11/40607

    摘要： A method and apparatus for refreshing data in a dynamic random access memory (DRAM) cache memory in a computer system are provided to perform a data refresh operation without refresh penalty (e.g., delay in a processor). A data refresh operation is performed with respect to a DRAM cache memory by detecting a request address from a processor, stopping a normal refresh operation when the request address is detected, comparing the request address with TAG addresses stored in a TAG memory, generating refresh addresses to refresh data stored in the cache memory, each of which is generated based on an age of data corresponding to the refresh address, and performing a read/write operation on a wordline accessed by the request addresses and refreshing data on wordlines accessed by the refresh addresses, wherein the read/write operation and the refreshing of data are performed simultaneously.

    摘要翻译： 提供了一种用于刷新计算机系统中的动态随机存取存储器（DRAM）高速缓冲存储器中的数据的方法和装置，用于执行数据刷新操作而不刷新（例如处理器中的延迟）。 通过检测来自处理器的请求地址，当检测到请求地址时停止正常刷新操作，将请求地址与存储在TAG存储器中的TAG地址进行比较，生成刷新地址 刷新存储在高速缓冲存储器中的数据，其中每个基于与刷新地址相对应的数据的年龄生成，并且对由请求地址访问的字线执行读/写操作，并且通过刷新访问的字线刷新数据 地址，其中同时执行读/写操作和数据刷新。

    System and method for increasing the speed of memories
    8.
    发明授权
    System and method for increasing the speed of memories 有权
    提高记忆速度的系统和方法

    公开(公告)号：US06512683B2

    公开(公告)日：2003-01-28

    申请号：US09827071

    申请日：2001-04-05

    申请人： Louis L. Hsu ,  Li-Kong Wang ,  Toshiaki K. Kirihata

    发明人： Louis L. Hsu ,  Li-Kong Wang ,  Toshiaki K. Kirihata

    IPC分类号： G11C1500

    CPC分类号： G06F12/0895 ,  G06F12/0846 ,  G11C7/1042

    摘要： The speed of memories is increased by trading memory density (or area) for speed (or cycle time). An n by n memory array is used to reduce the memory cycle time by 1/n. For example, if an existing memory cycle time is 6 ns, in order to achieve a 3ns (or n=2) cycle time, a 2 by 2 memory array is used. Or, in order to achieve a 1ns cycle time (or n=6), then a 6 by 6 memory array is used.

    摘要翻译： 通过为速度（或循环时间）交易记忆密度（或面积）来提高记忆速度。 n n存储器阵列用于将存储器周期时间减少1 / n。 例如，如果现有存储器周期时间为6ns，为了实现3ns（或n = 2）周期时间，则使用2乘2存储器阵列。 或者，为了实现1ns周期时间（或n = 6），则使用6乘6存储器阵列。

    High performance semiconductor memory device with low power consumption
    9.
    发明授权
    High performance semiconductor memory device with low power consumption 有权
    高性能半导体存储器件，功耗低

    公开(公告)号：US06307805B1

    公开(公告)日：2001-10-23

    申请号：US09745227

    申请日：2000-12-21

    申请人： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

    发明人： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

    IPC分类号： G11C700

    CPC分类号： G11C8/08 ,  G11C11/418 ,  H01L27/11

    摘要： A semiconductor memory device accessed with wordlines and bitlines has memory cells which operate at high performance with lower power consumption and have a high density. Each of the memory cells has pass transistors connected to a corresponding wordline and a corresponding pair of bitlines, and the pass transistors are gated by a signal of the corresponding wordline. The semiconductor memory device includes a wordline drive unit for selectively driving the wordlines in response to a row address. A wordline driver in the wordline drive unit boosts a corresponding wordline in a positive direction when the corresponding wordline is activated to access the memory cell and boosts the corresponding wordline in a negative direction when the corresponding wordline is inactive. By boosting the wordline in the positive direction, the performance of the memory cells is enhanced, and by boosting the wordline in the negative direction, a leakage current in the pass transistors with a low-threshold voltage is prevented.

    摘要翻译： 用字线和位线访问的半导体存储器件具有以较低的功耗以高密度工作的高性能的存储单元。 每个存储单元具有连接到相应字线和相应的一对位线的传输晶体管，并且通过晶体管由相应字线的信号选通。 半导体存储器件包括用于响应于行地址选择性地驱动字线的字线驱动单元。 当对应的字线不活动时，字线驱动单元中的字线驱动器在相应的字线被激活以访问存储器单元并且在相反的方向上升高相应的字线时以正方向提升相应的字线。 通过在正方向上升压字线，增强了存储单元的性能，并且通过在负方向上升高字线，防止具有低阈值电压的通过晶体管中的漏电流。

    High performance multi-mesa field effect transistor
    10.
    发明授权
    High performance multi-mesa field effect transistor 失效
    高性能多台面场效应晶体管

    公开(公告)号：US5675164A

    公开(公告)日：1997-10-07

    申请号：US486221

    申请日：1995-06-07

    申请人： Timothy A. Brunner ,  Louis L. Hsu ,  Jack A. Mandelman ,  Li-Kong Wang

    发明人： Timothy A. Brunner ,  Louis L. Hsu ,  Jack A. Mandelman ,  Li-Kong Wang

    IPC分类号： G03F7/20 ,  H01L21/027 ,  H01L21/28 ,  H01L21/308 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

    CPC分类号： H01L21/28185 ,  H01L21/0273 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/42368 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/785 ,  G03F7/2022 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/518 ,  H01L29/7833

    摘要： A high performance transistor includes mesa structures in a conduction region, favoring corner conduction, together with lightly doped mesa structures and mid-gap gate material also favoring operation in a fully depleted mode. Mesa structures are formed at sub-lithographic size and pitch as recesses or by epitaxial growth together with exposure of a resist by an interference pattern generation with illuminating radiation and multiple exposures using a mask shifted by a sub-lithographic distance. For an NFET, conduction electron and hole distribution profiles in the mesa structures and gate capacitance are adjusted with dielectric thickness, including deposition of oxide from a liquid solution at room temperature. Transconductance may be altered by change of the aspect ratio of the mesa structures. Lightly doped drain structures are also formed at sub-lithographic sizes by self-aligned processes.

    摘要翻译： 高性能晶体管包括传导区域中的台面结构，有利于拐角传导，以及轻掺杂的台面结构和中间间隙栅极材料，还有利于在完全耗尽模式下的操作。 Mesa结构以亚光刻尺寸和间距形成为凹陷，或通过外延生长形成，同时通过具有照射辐射的干涉图案生成以及使用偏移了亚光刻距离的掩模的多次曝光来曝光抗蚀剂。 对于NFET，通过介电厚度调整台面结构和栅极电容中的导电电子和空穴分布特征，包括在室温下从液体溶液中沉积氧化物。 跨导可以通过台面结构的纵横比的变化来改变。 轻掺杂漏极结构也通过自对准工艺以亚光刻尺寸形成。