公开(公告)号：US6141268A

公开(公告)日：2000-10-31

申请号：US348314

申请日：1999-07-07

申请人： Lidong Chen ,  Arun Achynthan ,  John Wu

发明人： Lidong Chen ,  Arun Achynthan ,  John Wu

IPC分类号： G11C11/408 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/846 ,  G11C11/408 ,  G11C11/4087

摘要： This invention describes a column redundancy arrangement in a DRAM that minimizes the timing difference between a normal and a redundant column path. A semiconductor memory device comprises memory elements arranged in rows and columns. The memory elements are accessed by energizing one or more rows and columns. A first and a second group of normal column drivers are provided for energizing associated normal memory columns in response to respective ones of column select signals. Further, a first and second redundant column driver are provided for energizing associated redundant memory columns upon receipt of a column select signal along a redundancy select line. A plurality of programmable switches are associated with the normal column drivers, for selectively steering respective ones of the column select signals to associated column drivers or the first or second of the redundant column drivers.

摘要翻译： 本发明描述了DRAM中的列冗余布置，其使正常和冗余列路径之间的定时差最小化。 半导体存储器件包括以行和列排列的存储元件。 通过激励一个或多个行和列来访问存储器元件。 提供第一组和第二组正常列驱动器，用于响应于列选择信号中的相应的一个列选择信号来激励相关的正常存储器列。 此外，第一和第二冗余列驱动器被提供用于在沿着冗余选择线接收列选择信号时激励相关联的冗余存储器列。 多个可编程开关与正常列驱动器相关联，用于将列选择信号中的相应列选择性地转向相关联的列驱动器或第一或第二冗余列驱动器。