Maintain power signature controller at power interface of PoE or PoDL system

    公开(公告)号:US10263794B2

    公开(公告)日:2019-04-16

    申请号:US15582445

    申请日:2017-04-28

    Abstract: The invention pertains to systems where DC power is supplied by a PSE to a PD, such as over differential data wire pairs. IEEE standards require a minimum current to be drawn from the PD in order for the PSE to continue supplying the DC voltage. If the PD is in a low power mode, the PSE will normally discontinue supplying the DC voltage, which then requires a new detection and classification routine for powering up again. To avoid this, a “maintain power signature” controller provides a periodic current pulse by a current source connected between the PD input and the PD's full bridge rectifier. Any droop in the DC voltage that reverse biases the full bridge rectifier while the PD is in its low power mode will not affect the current pulse, so the PSE continues to supply the DC voltage.

    MAINTAIN POWER SIGNATURE CONTROLLER AT POWER INTERFACE OF PoE OR PoDL SYSTEM

    公开(公告)号:US20170338969A1

    公开(公告)日:2017-11-23

    申请号:US15582445

    申请日:2017-04-28

    CPC classification number: H04L12/10 G06F1/26 H04L12/40045

    Abstract: The invention pertains to systems where DC power is supplied by a PSE to a PD, such as over differential data wire pairs. IEEE standards require a minimum current to be drawn from the PD in order for the PSE to continue supplying the DC voltage. If the PD is in a low power mode, the PSE will normally discontinue supplying the DC voltage, which then requires a new detection and classification routine for powering up again. To avoid this, a “maintain power signature” controller provides a periodic current pulse by a current source connected between the PD input and the PD's full bridge rectifier. Any droop in the DC voltage that reverse biases the full bridge rectifier while the PD is in its low power mode will not affect the current pulse, so the PSE continues to supply the DC voltage.

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