公开(公告)号：US5453388A

公开(公告)日：1995-09-26

申请号：US132941

申请日：1993-10-07

申请人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

发明人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L21/266 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L29/7883 ,  H01L27/115

摘要： Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

摘要翻译： 公开了使用片上电压倍增器电路仅需要5伏外部源的闪速EEPROM单元，以提供在编程和擦除模式期间实现Fowler-Nordheim隧穿所需的高电压。 浮置栅极和控制栅极之间以及浮置栅极和漏极区域之间的介电层的性质不同，以便于浮动栅极的编程和擦除。 还公开了一种通过在浮动栅极和控制栅极之间形成绝缘层以使电容低于浮置栅极和漏极区域之间的绝缘层的电容的电容来产生快闪EEPROM单元的方法。

公开(公告)号：US5373465A

公开(公告)日：1994-12-13

申请号：US132942

申请日：1993-10-07

申请人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

发明人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  G11C11/34 ,  G11C7/00

CPC分类号： H01L29/66825 ,  H01L29/7883 ,  H01L27/115

摘要： Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

公开(公告)号：US5317179A

公开(公告)日：1994-05-31

申请号：US764019

申请日：1991-09-23

申请人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

发明人： Ling Chen ,  Tien-ler Lin ,  Albert Wu

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/68 ,  H01L29/34 ,  H01L29/78

CPC分类号： H01L29/66825 ,  H01L29/7883 ,  H01L27/115

摘要： Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.

摘要翻译： 公开了使用片上电压倍增器电路仅需要5伏外部源的闪速EEPROM单元，以提供在编程和擦除模式期间实现Fowler-Nordheim隧穿所需的高电压。 浮置栅极和控制栅极之间以及浮置栅极和漏极区域之间的介电层的性质不同，以便于浮动栅极的编程和擦除。 还公开了一种通过在浮动栅极和控制栅极之间形成绝缘层以使电容低于浮置栅极和漏极区域之间的绝缘层的电容的电容来产生快闪EEPROM单元的方法。

公开(公告)号：US5216268A

公开(公告)日：1993-06-01

申请号：US764013

申请日：1991-09-23

申请人： Ling Chen ,  Tien-ler Lin

发明人： Ling Chen ,  Tien-ler Lin

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L29/7883 ,  H01L27/115

摘要： Disclosed is a byte-erasable EEPROM memory cell which utilizes a five volt external source and a voltage multiplier circuit to program and erase a floating gate by means of electron tunneling. To prevent collapse of the voltage multiplier circuit a lightly doped drain region is incorporated preventing gate modulated junction breakdown, thereby preventing collapse of the voltage multiplier circuit. In addition, current flow through the channel separating a source region and the lightly doped drain region is controlled by a portion of a control gate and the floating gate, thereby allowing a higher erased cell threshold voltage. Also disclosed is a process for forming the lightly doped drain region by using the control gate as an effective sidewall spacer.

摘要翻译： 公开了一种字节可擦除EEPROM存储单元，其利用五伏外部源和电压倍增器电路来通过电子隧道对浮动栅极进行编程和擦除。 为了防止电压倍增器电路的崩溃，掺入了轻掺杂的漏极区域，防止栅极调制结击穿，从而防止电压倍增器电路的崩溃。 此外，通过分离源极区域和轻掺杂漏极区域的沟道的电流流动由控制栅极和浮置栅极的一部分控制，从而允许更高的擦除单元阈值电压。 还公开了通过使用控制栅极作为有效侧壁间隔物来形成轻掺杂漏极区的工艺。

公开(公告)号：US06614715B2

公开(公告)日：2003-09-02

申请号：US10206497

申请日：2002-07-25

申请人： Cheng-Chung Tsao ,  Tien-ler Lin

发明人： Cheng-Chung Tsao ,  Tien-ler Lin

IPC分类号： G11C800

CPC分类号： G11C7/1042

摘要： A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively. This sub-page programming technique greatly reduces the disturbance and programming time.

公开(公告)号：US06556508B2

公开(公告)日：2003-04-29

申请号：US10206474

申请日：2002-07-25

申请人： Cheng-Chung Tsao ,  Tien-ler Lin

发明人： Cheng-Chung Tsao ,  Tien-ler Lin

IPC分类号： G11C800

CPC分类号： G11C7/1042

摘要： A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively. This sub-page programming technique greatly reduces the disturbance and programming time.

公开(公告)号：US06469955B1

公开(公告)日：2002-10-22

申请号：US09718649

申请日：2000-11-21

申请人： Cheng-Chung Tsao ,  Tien-ler Lin

发明人： Cheng-Chung Tsao ,  Tien-ler Lin

IPC分类号： G11C800

CPC分类号： G11C7/1042

摘要： A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively. This sub-page programming technique greatly reduces the disturbance and programming time.

摘要翻译： 非易失性半导体存储器包括以列和行排列的多个存储单元，多个字线，多个位线，多个输出缓冲器和分组在多个子页中的多个页缓冲器。 每个页面缓冲器通过第一列解码器电路连接到对应的位线，并通过第二列解码器电路连接到一个对应的输出缓冲器。 这种结构允许外围控制电路将存储在第一子页面的页面缓冲器中的数据输出到输出缓冲器中，同时将位线数据锁定到第二子页面的页面缓冲器中。 因此，该架构能够同时执行不同子页面的页面缓冲器数据的读取和更新。 两组地址寄存器用于存储编程的起始和结束地址。 在编程期间，只有位于起始地址和结束地址之间的子页将被连续编程。 这种子页面编程技术大大减少了干扰和编程时间。