公开(公告)号：US20090128232A1

公开(公告)日：2009-05-21

申请号：US11941869

申请日：2007-11-16

申请人： Liping Deng ,  Tiejun Dai ,  Haidong Guo ,  Chieh-Chien Lin ,  Yu-Shen Yang

发明人： Liping Deng ,  Tiejun Dai ,  Haidong Guo ,  Chieh-Chien Lin ,  Yu-Shen Yang

IPC分类号： H03F3/00 ,  H04N5/335

CPC分类号： H03F3/005 ,  H03F3/45183 ,  H03F3/68

摘要： A switch-capacitor (“SC”) amplifier includes a two-stage operational amplifier (“OP-AMP”), an input SC network, and a feedback SC network. The two-stage OP-AMP includes a first OP-AMP stage having an output coupled to an input of a second OP-AMP stage. The input SC network is coupled to an input of the first OP-AMP stage. The feedback SC network is configured to selectively couple the output of the first OP-AMP stage to the input of the first OP-AMP stage during a first phase of operation of the scamplifier and to couple an output of the second OP-AMP stage to the input of the first OP-AMP stage during a second phase of operation of the SC amplifier.

摘要翻译： 开关电容器（“SC”）放大器包括两级运算放大器（“OP-AMP”），输入SC网络和反馈SC网络。 两级OP-AMP包括具有耦合到第二OP-AMP级的输入的输出的第一OP-AMP级。 输入SC网络耦合到第一OP-AMP级的输入端。 反馈SC网络被配置为在放大器的第一操作阶段期间将第一OP-AMP级的输出选择性地耦合到第一OP-AMP级的输入，并且将第二OP-AMP级的输出耦合到 在SC放大器的第二操作阶段期间，第一OP-AMP级的输入。

公开(公告)号：US07639073B2

公开(公告)日：2009-12-29

申请号：US11941869

申请日：2007-11-16

申请人： Liping Deng ,  Tiejun Dai ,  Haidong Guo ,  Chieh-Chien Lin ,  Yu-Shen Yang

发明人： Liping Deng ,  Tiejun Dai ,  Haidong Guo ,  Chieh-Chien Lin ,  Yu-Shen Yang

IPC分类号： H03F1/02

CPC分类号： H03F3/005 ,  H03F3/45183 ,  H03F3/68

摘要： A switch-capacitor (“SC”) amplifier includes a two-stage operational amplifier (“OP-AMP”), an input SC network, and a feedback SC network. The two-stage OP-AMP includes a first OP-AMP stage having an output coupled to an input of a second OP-AMP stage. The input SC network is coupled to an input of the first OP-AMP stage. The feedback SC network is configured to selectively couple the output of the first OP-AMP stage to the input of the first OP-AMP stage during a first phase of operation of the SC amplifier and to couple an output of the second OP-AMP stage to the input of the first OP-AMP stage during a second phase of operation of the SC amplifier.

摘要翻译： 开关电容器（“SC”）放大器包括两级运算放大器（“OP-AMP”），输入SC网络和反馈SC网络。 两级OP-AMP包括具有耦合到第二OP-AMP级的输入的输出的第一OP-AMP级。 输入SC网络耦合到第一OP-AMP级的输入端。 反馈SC网络被配置为在SC放大器的第一操作阶段期间将第一OP-AMP级的输出选择性地耦合到第一OP-AMP级的输入，并且耦合第二OP-AMP级的输出 在SC放大器的第二操作阶段期间到第一OP-AMP级的输入。

公开(公告)号：US20120198399A1

公开(公告)日：2012-08-02

申请号：US13017864

申请日：2011-01-31

申请人： Sean Arash Safarpour ,  Duncan Philip Norman Smith ,  Yu-Shen Yang ,  Andreas Veneris

发明人： Sean Arash Safarpour ,  Duncan Philip Norman Smith ,  Yu-Shen Yang ,  Andreas Veneris

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： The present invention provides a system, method and computer program for determining constraint errors in hardware design debugging. The invention may be included as part of a complete verification solution. The method involves applying a diagnostic technique such that under-constrained problems are identified by adding a model-free error suspect or error candidate on the primary input signals (or other signals where constraints or stimuli are usually added). The present invention also provides a system, method and computer program that enables hardware design correction, consisting of the use of generating correction waveforms for identifying one or more corrections at the gate level and/or logic level of the hardware design. A number of different diagnostic techniques can be used in this way for example, include simulation-based techniques, BDD-based techniques, SAT-based techniques and path tracing. The method described can be implemented as part of a debugging computer system or computer program, including an automated debugger. The method described herein can also be implemented into a design correction engine that is operable to generate correction waveforms for each of the under constrained signals to provide to a user or automated system or computer program deeper insight for under-constrained problems. Furthermore, under-constrained signals may be combined with one or more correction waveforms to provide a software fix or external fix to a fabricated chip by providing a value sequence that is operable to avoid an error or bug in the fabricated chip.

摘要翻译： 本发明提供一种用于确定硬件设计调试中的约束误差的系统，方法和计算机程序。 本发明可以作为完整验证解决方案的一部分被包括。 该方法涉及应用诊断技术，使得通过在主要输入信号（或通常添加约束或刺激的其他信号）中添加无模型误差疑问或错误候选来识别受限制的问题。 本发明还提供了一种能够进行硬件设计校正的系统，方法和计算机程序，其包括使用产生校正波形来识别硬件设计的门级和/或逻辑电平处的一个或多个校正。 可以以这种方式使用许多不同的诊断技术，例如，包括基于模拟的技术，基于BDD的技术，基于SAT的技术和路径跟踪。 所描述的方法可以被实现为调试计算机系统或计算机程序的一部分，包括自动调试器。 本文描述的方法还可以被实现为设计校正引擎，其可操作以产生每个受限信号的校正波形，以向用户或自动化系统或计算机程序提供对于受限制问题的更深入的洞察。 此外，欠约束信号可以与一个或多个校正波形组合，以通过提供可操作以避免制造的芯片中的错误或错误的值序列来向制造的芯片提供软件固定或外部固定。