SWITCHED-CAPACITOR AMPLIFIER WITH IMPROVED RESET PHASE
    1.
    发明申请
    SWITCHED-CAPACITOR AMPLIFIER WITH IMPROVED RESET PHASE 有权
    具有改进复位相位的开关电容放大器

    公开(公告)号:US20090128232A1

    公开(公告)日:2009-05-21

    申请号:US11941869

    申请日:2007-11-16

    IPC分类号: H03F3/00 H04N5/335

    摘要: A switch-capacitor (“SC”) amplifier includes a two-stage operational amplifier (“OP-AMP”), an input SC network, and a feedback SC network. The two-stage OP-AMP includes a first OP-AMP stage having an output coupled to an input of a second OP-AMP stage. The input SC network is coupled to an input of the first OP-AMP stage. The feedback SC network is configured to selectively couple the output of the first OP-AMP stage to the input of the first OP-AMP stage during a first phase of operation of the scamplifier and to couple an output of the second OP-AMP stage to the input of the first OP-AMP stage during a second phase of operation of the SC amplifier.

    摘要翻译: 开关电容器(“SC”)放大器包括两级运算放大器(“OP-AMP”),输入SC网络和反馈SC网络。 两级OP-AMP包括具有耦合到第二OP-AMP级的输入的输出的第一OP-AMP级。 输入SC网络耦合到第一OP-AMP级的输入端。 反馈SC网络被配置为在放大器的第一操作阶段期间将第一OP-AMP级的输出选择性地耦合到第一OP-AMP级的输入,并且将第二OP-AMP级的输出耦合到 在SC放大器的第二操作阶段期间,第一OP-AMP级的输入。

    Switched-capacitor amplifier with improved reset phase
    2.
    发明授权
    Switched-capacitor amplifier with improved reset phase 有权
    开关电容放大器具有改善的复位阶段

    公开(公告)号:US07639073B2

    公开(公告)日:2009-12-29

    申请号:US11941869

    申请日:2007-11-16

    IPC分类号: H03F1/02

    摘要: A switch-capacitor (“SC”) amplifier includes a two-stage operational amplifier (“OP-AMP”), an input SC network, and a feedback SC network. The two-stage OP-AMP includes a first OP-AMP stage having an output coupled to an input of a second OP-AMP stage. The input SC network is coupled to an input of the first OP-AMP stage. The feedback SC network is configured to selectively couple the output of the first OP-AMP stage to the input of the first OP-AMP stage during a first phase of operation of the SC amplifier and to couple an output of the second OP-AMP stage to the input of the first OP-AMP stage during a second phase of operation of the SC amplifier.

    摘要翻译: 开关电容器(“SC”)放大器包括两级运算放大器(“OP-AMP”),输入SC网络和反馈SC网络。 两级OP-AMP包括具有耦合到第二OP-AMP级的输入的输出的第一OP-AMP级。 输入SC网络耦合到第一OP-AMP级的输入端。 反馈SC网络被配置为在SC放大器的第一操作阶段期间将第一OP-AMP级的输出选择性地耦合到第一OP-AMP级的输入,并且耦合第二OP-AMP级的输出 在SC放大器的第二操作阶段期间到第一OP-AMP级的输入。

    OP-AMP sharing with input and output reset
    3.
    发明授权
    OP-AMP sharing with input and output reset 有权
    OP-AMP共享输入和输出复位

    公开(公告)号:US08120423B2

    公开(公告)日:2012-02-21

    申请号:US12960858

    申请日:2010-12-06

    IPC分类号: H03F1/02

    CPC分类号: H03F3/45 H03F3/005

    摘要: An operational amplifier with two pairs of differential inputs for use with an input switch capacitor network. The operational amplifier has reset devices for resetting the second pair of differential inputs while amplifying the first pair of differential inputs, and for resetting the first pair of differential inputs while amplifying the second pair of differential inputs for reducing memory effect in electronic circuits. In an embodiment, the amplifier has an additional reset device for resetting the outputs during a prophase of amplifying the first pair of differential inputs and a prophase of amplifying the second pair of differential inputs.

    摘要翻译: 具有两对差分输入的运算放大器,用于与输入开关电容网络一起使用。 运算放大器具有复位装置,用于复位第二对差分输入,同时放大第一对差分输入,并用于复位第一对差分输入,同时放大第二对差分输入,以减少电子电路中的记忆效应。 在一个实施例中,放大器具有用于在放大第一对差分输入的前期期间复位输出的附加复位装置以及放大第二对差分输入的前期。

    HYBRID ANALOG-TO-DIGITAL CONVERTER HAVING MULTIPLE ADC MODES
    4.
    发明申请
    HYBRID ANALOG-TO-DIGITAL CONVERTER HAVING MULTIPLE ADC MODES 有权
    具有多种ADC模式的混合模数转换器

    公开(公告)号:US20140008515A1

    公开(公告)日:2014-01-09

    申请号:US13543470

    申请日:2012-07-06

    IPC分类号: H03M1/38 H03M1/14 H01L27/146

    CPC分类号: H03M1/145 H03M1/466 H03M1/56

    摘要: A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage.

    摘要翻译: 公开了一种具有用于产生数字信号位的逐次逼近寄存器(SAR)ADC模式和用于产生数字信号的附加位的斜坡ADC模式的混合ADC。 当处于SAR ADC模式时,控制电路被配置为禁止斜坡信号发生器; 禁用计数器 并且使能寄存器来控制偏移级以设置提供给ADC的比较器的输入的偏移电压的幅度。 当处于斜坡ADC模式时,控制电路被配置为使得斜坡信号发生器能够向比较器的输入端提供斜坡信号; 使计数器响应于比较器的输出开始提供数字计数; 并禁用寄存器,使偏移级不提供偏移电压。

    LIGHT SOURCE FREQUENCY DETECTION CIRCUIT USING BIPOLAR TRANSISTOR
    5.
    发明申请
    LIGHT SOURCE FREQUENCY DETECTION CIRCUIT USING BIPOLAR TRANSISTOR 有权
    使用双极晶体管的光源频率检测电路

    公开(公告)号:US20090128660A1

    公开(公告)日:2009-05-21

    申请号:US11942604

    申请日:2007-11-19

    IPC分类号: G01J1/18 H04N5/217

    摘要: An apparatus for measuring the power frequency of a light source includes a photo-sensitive transistor, a modulators and a logic unit. The photo-sensitive transistor generates an electrical signal that is responsive to light incident thereon from the light source. The modulator generates a modulated signal based on the electrical signal that toggles at a rate substantially proportional to the power frequency of the light source. The logic unit is coupled to receive the modulated signal and determine its toggling frequency.

    摘要翻译: 用于测量光源的功率频率的装置包括光敏晶体管,调制器和逻辑单元。 光敏晶体管产生响应于从光源入射到其上的光的电信号。 调制器基于电信号产生调制信号,该电信号以基本上与光源的功率频率成比例的速率切换。 逻辑单元被耦合以接收调制信号并确定其切换频率。

    Light source frequency detection circuit using bipolar transistor
    6.
    发明授权
    Light source frequency detection circuit using bipolar transistor 有权
    光源频率检测电路采用双极晶体管

    公开(公告)号:US07847834B2

    公开(公告)日:2010-12-07

    申请号:US11942604

    申请日:2007-11-19

    IPC分类号: H04N9/73

    摘要: An apparatus for measuring the power frequency of a light source includes a photo-sensitive transistor, a modulators and a logic unit. The photo-sensitive transistor generates an electrical signal that is responsive to light incident thereon from the light source. The modulator generates a modulated signal based on the electrical signal that toggles at a rate substantially proportional to the power frequency of the light source. The logic unit is coupled to receive the modulated signal and determine its toggling frequency.

    摘要翻译: 用于测量光源的功率频率的装置包括光敏晶体管,调制器和逻辑单元。 光敏晶体管产生响应于从光源入射到其上的光的电信号。 调制器基于电信号产生调制信号,该电信号以基本上与光源的功率频率成比例的速率切换。 逻辑单元被耦合以接收调制信号并确定其切换频率。

    Light source frequency detection circuit for image sensor
    8.
    发明申请
    Light source frequency detection circuit for image sensor 有权
    图像传感器光源频率检测电路

    公开(公告)号:US20090072126A1

    公开(公告)日:2009-03-19

    申请号:US11901212

    申请日:2007-09-14

    IPC分类号: G01R23/02 G01J1/44

    摘要: An apparatus for measuring the power frequency of a light source includes a photo-sensor, a modulator, and a logic unit. The photo-sensor generates an electrical signal that is responsive to light incident thereon from the light source. The modulator generates a modulated signal based on the electrical signal that toggles at a rate substantially proportional to the power frequency of the light source. The logic unit is coupled to receive the modulated signal and determine its toggling frequency.

    摘要翻译: 用于测量光源的功率频率的装置包括光传感器,调制器和逻辑单元。 光传感器产生响应于从光源入射到其上的光的电信号。 调制器基于电信号产生调制信号,该电信号以基本上与光源的功率频率成比例的速率切换。 逻辑单元被耦合以接收调制信号并确定其切换频率。

    Hybrid analog-to-digital converter having multiple ADC modes
    9.
    发明授权
    Hybrid analog-to-digital converter having multiple ADC modes 有权
    具有多种ADC模式的混合模数转换器

    公开(公告)号:US08933385B2

    公开(公告)日:2015-01-13

    申请号:US13543470

    申请日:2012-07-06

    IPC分类号: G01J1/44 H03M1/12 H03M1/38

    CPC分类号: H03M1/145 H03M1/466 H03M1/56

    摘要: A hybrid ADC having a successive approximation register (SAR) ADC mode for generating a bit of a digital signal and a ramp ADC mode for generating an additional bit of the digital signal is disclosed. When in the SAR ADC mode, a control circuit is configured to disable a ramp signal generator; disable a counter; and enable a register to control an offset stage to set the magnitude of an offset voltage that is provided to an input of a comparator of the ADC. When in the ramp ADC mode, the control circuit is configured to enable the ramp signal generator to provide a ramp signal to the input of the comparator; enable the counter to begin providing the digital count in response to the output of the comparator; and disable the register so that the offset stage is not providing the offset voltage.

    摘要翻译: 公开了一种具有用于产生数字信号位的逐次逼近寄存器(SAR)ADC模式和用于产生数字信号的附加位的斜坡ADC模式的混合ADC。 当处于SAR ADC模式时,控制电路被配置为禁止斜坡信号发生器; 禁用计数器 并且使能寄存器来控制偏移级以设置提供给ADC的比较器的输入的偏移电压的幅度。 当处于斜坡ADC模式时,控制电路被配置为使得斜坡信号发生器能够向比较器的输入端提供斜坡信号; 使计数器响应于比较器的输出开始提供数字计数; 并禁用寄存器,使偏移级不提供偏移电压。

    OP-AMP SHARING WITH INPUT AND OUTPUT RESET
    10.
    发明申请
    OP-AMP SHARING WITH INPUT AND OUTPUT RESET 有权
    OP-AMP共享与输入和输出复位

    公开(公告)号:US20110148523A1

    公开(公告)日:2011-06-23

    申请号:US12960858

    申请日:2010-12-06

    IPC分类号: H03F3/45

    CPC分类号: H03F3/45 H03F3/005

    摘要: An operational amplifier with two pairs of differential inputs for use with an input switch capacitor network. The operational amplifier has reset devices for resetting the second pair of differential inputs while amplifying the first pair of differential inputs, and for resetting the first pair of differential inputs while amplifying the second pair of differential inputs for reducing memory effect in electronic circuits. In an embodiment, the amplifier has an additional reset device for resetting the outputs during a prophase of amplifying the first pair of differential inputs and a prophase of amplifying the second pair of differential inputs.

    摘要翻译: 具有两对差分输入的运算放大器,用于与输入开关电容网络一起使用。 运算放大器具有复位装置,用于复位第二对差分输入,同时放大第一对差分输入,并用于复位第一对差分输入,同时放大第二对差分输入,以减少电子电路中的记忆效应。 在一个实施例中,放大器具有用于在放大第一对差分输入的前期期间复位输出的附加复位装置以及放大第二对差分输入的前期。