摘要:
A tuned low-noise amplifier is disclosed. A device in accordance with the present invention comprises a first current source, a second current source, a comparator, coupled to the first current source and the second current source, for providing a control signal, and a third current source, receiving the control signal and coupled to the tuned low-noise amplifier, wherein a current in the third current source is proportional to a current in the first current source and the second current source, where values of the first current source, the second current source, and the third current source are based on a quasi-Proportional-To-Absolute-Temperature (PTAT) curve.
摘要:
A GPS receiver with automatic mode-setting and power ramping circuitry is disclosed. AGPS receiver in accordance with the present invention comprises a first switch network, comprising a plurality of transistors, a first plurality of circuit components, coupled to the first switch network, wherein the switch network selects paths through the circuit components to generate a Power On Signal (POS) and ramp power to the GPS receiver, a plurality of test points, coupled to circuitry within the GPS receiver, wherein the test points are used to test intermediate stages of output of the GPS receiver, a second plurality of circuit components, each circuit component coupled to a corresponding test point in a respective manner, wherein the circuit components create outputs used in initialization of the GPS receiver, and a second switch network, coupled between the circuitry in the GPS receiver and the plurality of test points, for selectively switching the plurality of test points from being used to test intermediate stages of output of the GPS receiver and creating outputs used in initialization.
摘要:
A two-bit offset canceling A/D converter with improved common mode rejection and threshold sensitivity for use in GPS receivers. A device in accordance with the present invention comprises a level shifter, the level shifter receiving a positive signal and a negative signal, the level shifter shifting the positive signal and the negative signal such that a difference between the positive signal and the negative signal is larger than a threshold value, and a comparator, coupled to the level shifter, the comparator providing as outputs of the comparators a sign bit and two magnitude bits wherein the comparator comprises a plurality of switched capacitor amplifiers.
摘要:
A two-bit offset canceling A/D converter with improved common mode rejection and threshold sensitivity for use in GPS receivers. A device in accordance with the present invention comprises a level shifter, the level shifter receiving a positive signal and a negative signal, the level shifter shifting the positive signal and the negative signal such that a difference between the positive signal and the negative signal is larger than a threshold value, and a comparator, coupled to the level shifter, the comparator providing as outputs of the comparators a sign bit and two magnitude bits wherein the comparator comprises a plurality of switched capacitor amplifiers.
摘要:
A two-bit offset canceling A/D converter with improved common mode rejection and threshold sensitivity for use in GPS receivers. A device in accordance with the present invention comprises a level shifter, the level shifter receiving a positive signal and a negative signal, the level shifter shifting the positive signal and the negative signal such that a difference between the positive signal and the negative signal is larger than a threshold value, and a comparator, coupled to the level shifter, the comparator providing as outputs of the comparators a sign bit and two magnitude bits wherein the comparator comprises a plurality of switched capacitor amplifiers.
摘要:
A tuned low-noise amplifier is disclosed. A device in accordance with the present invention comprises a first current source, a second current source, a comparator, coupled to the first current source and the second current source, for providing a control signal, and a third current source, receiving the control signal and coupled to the tuned low-noise amplifier, wherein a current in the third current source is proportional to a current in the first current source and the second current source, where values of the first current source, the second current source, and the third current source are based on a quasi-Proportional-To-Absolute-Temperature (PTAT) curve.
摘要:
A GPS receiver with automatic mode-setting and power ramping circuitry is disclosed. AGPS receiver in accordance with the present invention comprises a first switch network, comprising a plurality of transistors, a first plurality of circuit components, coupled to the first switch network, wherein the switch network selects paths through the circuit components to generate a Power On Signal (POS) and ramp power to the GPS receiver, a plurality of test points, coupled to circuitry within the GPS receiver, wherein the test points are used to test intermediate stages of output of the GPS receiver, a second plurality of circuit components, each circuit component coupled to a corresponding test point in a respective manner, wherein the circuit components create outputs used in initialization of the GPS receiver, and a second switch network, coupled between the circuitry in the GPS receiver and the plurality of test points, for selectively switching the plurality of test points from being used to test intermediate stages of output of the GPS receiver and creating outputs used in initialization.
摘要:
A two-bit offset canceling A/D converter with improved common mode rejection and threshold sensitivity for use in GPS receivers. A device in accordance with the present invention comprises a level shifter, the level shifter receiving a positive signal and a negative signal, the level shifter shifting the positive signal and the negative signal such that a difference between the positive signal and the negative signal is larger than a threshold value, and a comparator, coupled to the level shifter, the comparator providing as outputs of the comparators a sign bit and two magnitude bits wherein the comparator comprises a plurality of switched capacitor amplifiers.