TWO-BIT OFFSET CANCELLING A/D CONVERTER WITH IMPROVED COMMON MODE REJECTION AND THRESHOLD SENSITIVITY
    3.
    发明申请
    TWO-BIT OFFSET CANCELLING A/D CONVERTER WITH IMPROVED COMMON MODE REJECTION AND THRESHOLD SENSITIVITY 有权
    双位偏移取消A / D转换器,具有改进的共模抑制和阈值灵敏度

    公开(公告)号:US20070080839A1

    公开(公告)日:2007-04-12

    申请号:US11611276

    申请日:2006-12-15

    IPC分类号: H03M1/66

    摘要: A two-bit offset canceling A/D converter with improved common mode rejection and threshold sensitivity for use in GPS receivers. A device in accordance with the present invention comprises a level shifter, the level shifter receiving a positive signal and a negative signal, the level shifter shifting the positive signal and the negative signal such that a difference between the positive signal and the negative signal is larger than a threshold value, and a comparator, coupled to the level shifter, the comparator providing as outputs of the comparators a sign bit and two magnitude bits wherein the comparator comprises a plurality of switched capacitor amplifiers.

    摘要翻译: 具有改进的共模抑制和阈值灵敏度的两位偏移消除A / D转换器,用于GPS接收机。 根据本发明的装置包括电平移位器,电平移位器接收正信号和负信号,电平移位器将正信号和负信号移位,使得正信号和负信号之间的差较大 比较器,耦合到电平移位器,比较器提供比较器的输出,符号位和两个幅度位,其中比较器包括多个开关电容放大器。

    Two-bit offset cancelling A/D converter with improved common mode rejection and threshold sensitivity
    4.
    发明申请
    Two-bit offset cancelling A/D converter with improved common mode rejection and threshold sensitivity 失效
    具有改进的共模抑制和阈值灵敏度的两位偏移消除A / D转换器

    公开(公告)号:US20060103565A1

    公开(公告)日:2006-05-18

    申请号:US11271729

    申请日:2005-11-10

    IPC分类号: H03M1/12

    摘要: A two-bit offset canceling A/D converter with improved common mode rejection and threshold sensitivity for use in GPS receivers. A device in accordance with the present invention comprises a level shifter, the level shifter receiving a positive signal and a negative signal, the level shifter shifting the positive signal and the negative signal such that a difference between the positive signal and the negative signal is larger than a threshold value, and a comparator, coupled to the level shifter, the comparator providing as outputs of the comparators a sign bit and two magnitude bits wherein the comparator comprises a plurality of switched capacitor amplifiers.

    摘要翻译: 具有改进的共模抑制和阈值灵敏度的两位偏移消除A / D转换器,用于GPS接收机。 根据本发明的装置包括电平移位器,电平移位器接收正信号和负信号,电平移位器将正信号和负信号移位,使得正信号和负信号之间的差较大 比较器,耦合到电平移位器,比较器提供比较器的输出,符号位和两个幅度位,其中比较器包括多个开关电容放大器。

    Linearized and delay compensated all CMOS VCO
    5.
    发明授权
    Linearized and delay compensated all CMOS VCO 失效
    线性化和延迟补偿的所有CMOS VCO

    公开(公告)号:US5212459A

    公开(公告)日:1993-05-18

    申请号:US960534

    申请日:1992-10-13

    IPC分类号: H03K3/0231

    CPC分类号: H03K3/0231

    摘要: The present invention provides a linearized and delay compensated all CMOS voltage controlled oscillator. A transconductance converter receives a control voltage input and provides a control current to a current controlled ramping circuit that is responsible for providing two ramping voltage outputs to the positive inputs of two comparators. These comparators compare the ramping voltages to a threshold voltage and provide pulses to a latch when the ramping voltages cross the threshold voltage. The latch provides the oscillating output of the circuit which is fed back to the current controlled ramping circuit for switching purposes. A compensation loop receives both the oscillating output of the latch and the control current as inputs and provides the threshold voltage to the comparators. The compensation loop contains a similar current controlled ramping circuit which provides ramping outputs identical to those of the first current controlled ramping circuit. Track-and-hold circuits triggered by the oscillating outputs provide the peak voltages of the ramping outputs through a low-pass filter to the negative input of a difference amplifier. An external reference voltage is supplied to the positive input of the difference amplifier and the output of the difference amplifier is provided as the threshold voltage to the comparators. The effects of the comparator delay and the latch delay are cancelled out by the compensation loop.

    摘要翻译: 本发明提供一种线性化和延迟补偿的全部CMOS压控振荡器。 跨导转换器接收控制电压输入并向控制的电流斜坡电路提供控制电流,该电路负责向两个比较器的正输入端提供两个斜坡电压输出。 这些比较器将斜坡电压与阈值电压进行比较,并且当斜坡电压跨越阈值电压时,向闩锁提供脉冲。 闩锁提供电路的振荡输出,其被反馈到电流控制的斜坡电路以用于切换目的。 补偿回路接收锁存器的振荡输出和控制电流作为输入,并将阈值电压提供给比较器。 补偿回路包含类似的电流控制斜坡电路,其提供与第一电流控制斜坡电路相同的斜坡输出。 由振荡输出触发的跟踪和保持电路通过低通滤波器向差分放大器的负输入提供斜坡输出的峰值电压。 外部参考电压被提供给差分放大器的正输入,差分放大器的输出作为阈值电压被提供给比较器。 比较器延迟和锁存延迟的影响由补偿回路消除。

    Linearized and delay compensated all CMOS VCO
    6.
    发明授权
    Linearized and delay compensated all CMOS VCO 失效
    线性化和延迟补偿的所有CMOS VCO

    公开(公告)号:US5155452A

    公开(公告)日:1992-10-13

    申请号:US792222

    申请日:1991-11-12

    IPC分类号: H03K4/12 H03K3/0231 H03L7/099

    CPC分类号: H03K3/0231

    摘要: The present invention provides a linearized and delay compensated all CMOS voltage controlled oscillator. A transconductance converter receives a control voltage input and provides a control current to a current controlled ramping circuit that is responsible for providing two ramping voltage outputs to the positive inputs of two comparators. These comparators compare the ramping voltages to a threshold voltage and provide pulses to a latch when the ramping voltages cross the threshold voltage. The latch provides the oscillating output of the circuit which is fed back to the current controlled ramping circuit for switching purposes. A compensation loop receives both the oscillating output of the latch and the control current as inputs and provides the threshold voltage to the comparators. The compensation loop contains a similar current controlled ramping circuit which provides ramping outputs identical to those of the first current controlled ramping circuit. Track-and-hold circuits triggered by the oscillating outputs provide the peak voltages of the ramping outputs through a low-pass filter to the negative input of a difference amplifier. An external reference voltage is supplied to the positive input of the difference amplifier and the output of the difference amplifier is provided as the threshold voltage to the comparators. The effects of the comparator delay and the latch delay are cancelled out by the compensation loop.

    摘要翻译: 本发明提供一种线性化和延迟补偿的全部CMOS压控振荡器。 跨导转换器接收控制电压输入并向控制的电流斜坡电路提供控制电流,该电路负责向两个比较器的正输入端提供两个斜坡电压输出。 这些比较器将斜坡电压与阈值电压进行比较,并且当斜坡电压跨越阈值电压时,向闩锁提供脉冲。 闩锁提供电路的振荡输出,其被反馈到电流控制的斜坡电路以用于切换目的。 补偿回路接收锁存器的振荡输出和控制电流作为输入,并将阈值电压提供给比较器。 补偿回路包含类似的电流控制斜坡电路,其提供与第一电流控制斜坡电路相同的斜坡输出。 由振荡输出触发的跟踪和保持电路通过低通滤波器向差分放大器的负输入提供斜坡输出的峰值电压。 外部参考电压被提供给差分放大器的正输入,差分放大器的输出作为阈值电压被提供给比较器。 比较器延迟和锁存延迟的影响由补偿回路消除。