公开(公告)号：US20240304269A1

公开(公告)日：2024-09-12

申请号：US18667099

申请日：2024-05-17

Applicant: Lodestar Licensing Group LLC

Inventor： Boon Hor Lam ,  Shawn M. Hilde ,  Karl L. Major ,  Garrett Harwell

IPC: G11C29/12 ,  G11C7/10 ,  G11C11/406 ,  G11C29/14 ,  G11C29/44

CPC classification number: G11C29/12015 ,  G11C7/1048 ,  G11C11/40615 ,  G11C29/14 ,  G11C29/44

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory device are configured to add variable delays to a command. The variable delays may be provided by a host device (e.g., a test equipment) using a test mode of the memory devices. Alternatively, the variable delays may be stored in nonvolatile memory (NVM) components of the memory devices. Further, mode registers of the memory devices may be set to indicate that the command is associated with the variable delays stored in the NVM components. Further, the memory devices may include delay components configured to add the variable delays to the command. Such variable delays facilitate staggered execution of the command across multiple memory devices so as to avoid (or mitigate) issues related to an instantaneous, large amount of current drawn from a power supply connected to the memory devices.

公开(公告)号：US11990195B2

公开(公告)日：2024-05-21

申请号：US17935057

申请日：2022-09-23

Applicant: Lodestar Licensing Group LLC

Inventor： Boon Hor Lam ,  Shawn M. Hilde ,  Karl L. Major ,  Garrett Harwell

IPC: G11C29/12 ,  G11C7/10 ,  G11C11/406 ,  G11C29/14 ,  G11C29/44

CPC classification number: G11C29/12015 ,  G11C7/1048 ,  G11C11/40615 ,  G11C29/14 ,  G11C29/44

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory device are configured to add variable delays to a command. The variable delays may be provided by a host device (e.g., a test equipment) using a test mode of the memory devices. Alternatively, the variable delays may be stored in nonvolatile memory (NVM) components of the memory devices. Further, mode registers of the memory devices may be set to indicate that the command is associated with the variable delays stored in the NVM components. Further, the memory devices may include delay components configured to add the variable delays to the command. Such variable delays facilitate staggered execution of the command across multiple memory devices so as to avoid (or mitigate) issues related to an instantaneous, large amount of current drawn from a power supply connected to the memory devices.