公开(公告)号：US20240386983A1

公开(公告)日：2024-11-21

申请号：US18671201

申请日：2024-05-22

Applicant: Lodestar Licensing Group LLC

Inventor： Keisuke Fujishiro ,  Yoshifumi Mochida

IPC: G11C29/42 ,  G11C7/10 ,  G11C8/12

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. A first latch may hold the encoded bit and provide it as a write parity bit to the memory array as part of a write operation. A second latch may hold a parity bit read from the memory array and the ECC circuit may generate a command signal based on that parity bit. A multiplexer latch may hold the encoded bit and provide a syndrome bit based on the command signal and the encoded bit. The syndrome bit may indicate if there is mismatch between the parity bit and the encoded bit. The logic which handles generating the syndrome bit may be separated from the logic tree.