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公开(公告)号：US20060279988A1
公开(公告)日：2006-12-14
申请号：US11193924
申请日：2005-07-28
申请人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
发明人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
IPC分类号： G11C16/04
CPC分类号： G11C16/26
摘要： A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.
摘要翻译： 用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。 存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。 参考矩阵耦合到存储器矩阵并具有参考单元。 逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。
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公开(公告)号：US07283396B2
公开(公告)日：2007-10-16
申请号：US11193924
申请日：2005-07-28
申请人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
发明人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.
摘要翻译： 用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。 存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。 参考矩阵耦合到存储器矩阵并具有参考单元。 逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。
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3.发明申请Method and apparatus for discharging a memory cell in a memory device after an erase operation 有权在擦除操作之后，用于在存储器件中放电存储单元的方法和装置公开(公告)号：US20070047325A1
公开(公告)日：2007-03-01
申请号：US11583625
申请日：2006-10-18
IPC分类号： G11C16/06
摘要： A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the second plate of the capacitor through a second discharge circuit. After the initial discharge, the method further includes completely discharging the first plate of the capacitor and the second plate of the capacitor by coupling both the first plate of the capacitor and the second plate of the capacitor to ground.
摘要翻译： 一种用于对存储器件中的存储单元进行放电的方法和装置。 在一个实施方式中，存储单元包括具有第一板和第二板的电容器，并且该方法包括首先通过第一放电电路对电容器的第一板进行放电，并通过第二放电电路对电容器的第二板进行放电。 在初始放电之后，该方法还包括通过将电容器的第一板和电容器的第二板耦合到地将电容器的第一板和电容器的第二板完全放电。
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4.发明授权Method and apparatus for discharging a memory cell in a memory device after an erase operation 有权在擦除操作之后，用于在存储器件中放电存储单元的方法和装置公开(公告)号：US07499334B2
公开(公告)日：2009-03-03
申请号：US11583625
申请日：2006-10-18
IPC分类号： G11C11/34
摘要： A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the second plate of the capacitor through a second discharge circuit. After the initial discharge, the method further includes completely discharging the first plate of the capacitor and the second plate of the capacitor by coupling both the first plate of the capacitor and the second plate of the capacitor to ground.
摘要翻译： 一种用于对存储器件中的存储单元进行放电的方法和装置。 在一个实施方式中，存储单元包括具有第一板和第二板的电容器，并且该方法包括首先通过第一放电电路对电容器的第一板进行放电，并通过第二放电电路对电容器的第二板进行放电。 在初始放电之后，该方法还包括通过将电容器的第一板和电容器的第二板耦合到地将电容器的第一板和电容器的第二板完全放电。
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公开(公告)号：US20060140010A1
公开(公告)日：2006-06-29
申请号：US11144174
申请日：2005-06-02
申请人： Lorenzo Bedarida , Fabio Caser , Simone Bartoli , Giorgio Oddone
发明人： Lorenzo Bedarida , Fabio Caser , Simone Bartoli , Giorgio Oddone
IPC分类号： G11C16/04
CPC分类号： G11C16/3454
摘要： A system and method for reducing soft-writing in a multilevel flash memory during read or verify includes a memory cell. A first and second reference cells are coupled to the memory cell and are configured to receive a first and a second voltage. A current comparison circuit is coupled to the first and second reference cells and to the memory cell and is configured to compare current flow through the memory cell with current flow through the first and second reference cells, and to determine whether the memory cell holds a first range of values while the first reference cell receives the first voltage, and if the memory cell does not hold the first range of values, to determine whether the memory cell holds a second range of values while the second reference cell receives the second voltage, thereby reducing soft-writing during the read operation.
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6.发明授权Compensated method to implement a high voltage discharge phase after erase pulse in a flash memory device 有权补偿方法在闪存器件中擦除脉冲后实现高电压放电相位公开(公告)号：US07177198B2
公开(公告)日：2007-02-13
申请号：US11123979
申请日：2005-05-06
IPC分类号： G11C11/34
CPC分类号： G11C16/14
摘要： A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk capacitor, and a second discharge circuit to a second plate of the gate-bulk capacitor, where the first plate represents the common gate node of the memory cell and the second plate represents the bulk-source node of the memory cell; and coupling the common gate node and the bulk-source node to ground to provide for a complete discharge. The current injected into the first plate approximately equals the current extracted from the second plate. In this manner, dangerous oscillations of the gate and bulk-source voltages as they go to ground are eliminated without complicated designs or voltage limitators, and without sacrificing the fast discharge after the erase operation. The reliability of the discharge operation is thus significantly improved.
摘要翻译： 一种闪速存储装置中的放电方法包括：在擦除操作之后启动存储单元的放电; 将第一放电电路耦合到栅极 - 体积电容器的第一板，以及将第二放电电路耦合到栅极 - 体积电容器的第二板，其中第一板表示存储单元的公共栅极节点，第二板表示 存储器单元的批量源节点; 并将公共栅极节点和体源节点耦合到地，以提供完全放电。 注入第一板的电流大约等于从第二板提取的电流。 以这种方式，在没有复杂设计或限压器的情况下，栅极和体源电压的危险振荡消除，而不会在擦除操作之后不牺牲快速放电。 因此，放电操作的可靠性显着提高。
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7.发明申请Compensated method to implement a high voltage discharge phase after erase pulse in a flash memory device 有权补偿方法在闪存器件中擦除脉冲后实现高电压放电相位公开(公告)号：US20060062063A1
公开(公告)日：2006-03-23
申请号：US11123979
申请日：2005-05-06
CPC分类号： G11C16/14
摘要： A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk capacitor, and a second discharge circuit to a second plate of the gate-bulk capacitor, where the first plate represents the common gate node of the memory cell and the second plate represents the bulk-source node of the memory cell; and coupling the common gate node and the bulk-source node to ground to provide for a complete discharge. The current injected into the first plate approximately equals the current extracted from the second plate. In this manner, dangerous oscillations of the gate and bulk-source voltages as they go to ground are eliminated without complicated designs or voltage limitators, and without sacrificing the fast discharge after the erase operation. The reliability of the discharge operation is thus significantly improved.
摘要翻译： 一种闪速存储装置中的放电方法包括：在擦除操作之后启动存储单元的放电; 将第一放电电路耦合到栅极 - 体积电容器的第一板，以及将第二放电电路耦合到栅极 - 体积电容器的第二板，其中第一板表示存储单元的公共栅极节点，第二板表示 存储器单元的批量源节点; 并将公共栅极节点和体源节点耦合到地，以提供完全放电。 注入第一板的电流大约等于从第二板提取的电流。 以这种方式，在没有复杂设计或限压器的情况下，栅极和体源电压的危险振荡消除，而不会在擦除操作之后不牺牲快速放电。 因此，放电操作的可靠性显着提高。
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8.发明授权公开(公告)号：US07522455B2
公开(公告)日：2009-04-21
申请号：US11144174
申请日：2005-06-02
IPC分类号： G11C11/34
CPC分类号： G11C16/3454
摘要： A system and method for reducing soft-writing in a multilevel flash memory during read or verify includes a memory cell. A first and second reference cells are coupled to the memory cell and are configured to receive a first and a second voltage. A current comparison circuit is coupled to the first and second reference cells and to the memory cell and is configured to compare current flow through the memory cell with current flow through the first and second reference cells, and to determine whether the memory cell holds a first range of values while the first reference cell receives the first voltage, and if the memory cell does not hold the first range of values, to determine whether the memory cell holds a second range of values while the second reference cell receives the second voltage, thereby reducing soft-writing during the read operation.
摘要翻译： 在读取或验证期间减少多级闪存中的软写入的系统和方法包括存储单元。 第一和第二参考单元耦合到存储单元，并被配置为接收第一和第二电压。 电流比较电路耦合到第一和第二参考单元和存储单元，并且被配置为将通过存储器单元的电流与通过第一和第二参考单元的电流进行比较，并且确定存储器单元是否保持第一 在第一参考单元接收到第一电压的同时，如果存储单元不保持第一范围的值，则确定存储单元是否在第二参考单元接收到第二电压时保持第二范围的值，从而 在读取操作期间减少软写入。
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公开(公告)号：US07864557B2
公开(公告)日：2011-01-04
申请号：US11529158
申请日：2006-09-28
IPC分类号： G11C17/00
CPC分类号： G11C16/22 , G11C2216/26
摘要： A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds to a portion of a block of the plurality of blocks. The OTP cell allows modification of the portion of the block when the OTP cell is in a first state and permanently prevents modification of the portion of the block when the OTP cell is in a second state. The OTP cell logic uses the plurality of OTP cells to select the portion of the block as corresponding to the OTP cell. This portion of the block is write protected when the OTP cell is placed in the second state.
摘要翻译： 公开了一种用于保护具有多个块的存储器不被修改的方法和系统。 该方法和系统包括提供与OTP单元耦合的多个一次可编程（OTP）单元和OTP单元逻辑。 多个OTP单元的OTP单元对应于多个块的块的一部分。 当OTP小区处于第一状态时，OTP小区允许修改块的部分，并且当OTP小区处于第二状态时永久地防止块的该部分的修改。 OTP单元逻辑使用多个OTP单元来选择与OTP单元相对应的块的该部分。 当OTP单元处于第二状态时，块的这一部分是写保护的。
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公开(公告)号：US07130209B2
公开(公告)日：2006-10-31
申请号：US11128648
申请日：2005-05-12
IPC分类号： G11C17/00
CPC分类号： G11C16/22 , G11C2216/26
摘要： A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds to a portion of a block of the plurality of blocks. The OTP cell allows modification of the portion of the block when the OTP cell is in a first state and permanently prevents modification of the portion of the block when the OTP cell is in a second state. The OTP cell logic uses the plurality of OTP cells to select the portion of the block as corresponding to the OTP cell. This portion of the block is write protected when the OTP cell is placed in the second state.
摘要翻译： 公开了一种用于保护具有多个块的存储器不被修改的方法和系统。 该方法和系统包括提供与OTP单元耦合的多个一次可编程（OTP）单元和OTP单元逻辑。 多个OTP单元的OTP单元对应于多个块的块的一部分。 当OTP小区处于第一状态时，OTP小区允许修改块的部分，并且当OTP小区处于第二状态时永久地防止修改块的部分。 OTP单元逻辑使用多个OTP单元来选择与OTP单元相对应的块的该部分。 当OTP单元处于第二状态时，块的这一部分是写保护的。
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