公开(公告)号：US07790522B2

公开(公告)日：2010-09-07

申请号：US12543630

申请日：2009-08-19

申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

IPC分类号： H01L21/00

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78 ,  H01L29/785 ,  Y10T428/12528

摘要： A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.

公开(公告)号：US20080220280A1

公开(公告)日：2008-09-11

申请号：US11682403

申请日：2007-03-06

申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

IPC分类号： B05D5/12 ,  H01L29/12

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78 ,  H01L29/785 ,  Y10T428/12528

摘要： A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.

摘要翻译： 半导体器件包括具有两个晶体取向的半导体材料。 半导体材料形成该器件的有效区域。 在两个晶体取向上形成器件沟道，其包括形成在半导体材料的第一晶体取向表面中的第一区域和形成在半导体材料的第二晶体取向表面中的第二区域，其中第一晶体取向表面形成 与第二晶体取向表面和器件通道的角度至少覆盖角度的交点。

公开(公告)号：US07777306B2

公开(公告)日：2010-08-17

申请号：US11682403

申请日：2007-03-06

申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78 ,  H01L29/785 ,  Y10T428/12528

摘要： A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.

摘要翻译： 半导体器件包括具有两个晶体取向的半导体材料。 半导体材料形成该器件的有效区域。 在两个晶体取向上形成器件沟道，其包括形成在半导体材料的第一晶体取向表面中的第一区域和形成在半导体材料的第二晶体取向表面中的第二区域，其中第一晶体取向表面形成 与第二晶体取向表面和器件通道的角度至少覆盖角度的交点。

公开(公告)号：US20090305472A1

公开(公告)日：2009-12-10

申请号：US12543630

申请日：2009-08-19

申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

IPC分类号： H01L21/762

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78 ,  H01L29/785 ,  Y10T428/12528

摘要： A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.

摘要翻译： 半导体器件包括具有两个晶体取向的半导体材料。 半导体材料形成该器件的有效区域。 在两个晶体取向上形成器件沟道，其包括形成在半导体材料的第一晶体取向表面中的第一区域和形成在半导体材料的第二晶体取向表面中的第二区域，其中第一晶体取向表面形成 与第二晶体取向表面和器件通道的角度至少覆盖角度的交点。

公开(公告)号：US20090175068A1

公开(公告)日：2009-07-09

申请号：US11969981

申请日：2008-01-07

申请人： Xu Ouyang ,  Louis C. Hsu

发明人： Xu Ouyang ,  Louis C. Hsu

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： An SRAM device comprising a pair of MCSFETs connected as access transistors (pass gates). An SRAM device design structure embodied or stored in a machine readable medium includes two MCSFETs connected as access transistors.

摘要翻译： 一种SRAM器件，包括连接作为存取晶体管（通孔）的一对MCSFET。 体现或存储在机器可读介质中的SRAM器件设计结构包括作为存取晶体管连接的两个MCSFET。

公开(公告)号：US08759175B2

公开(公告)日：2014-06-24

申请号：US13429556

申请日：2012-03-26

申请人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

发明人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/7881

摘要： A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.

摘要翻译： 具有增强的电容耦合系数比（CCCR）的闪速存储器结构可以以自对准方式制造，同时使用半导体衬底，该半导体衬底具有相对于围绕有源区域的隔离区域在孔内凹入的有源区域 。 闪速存储器结构包括不在隔离区上方升起的浮栅，并且优选地由具有U形的单层组成。 U形增强了电容耦合系数比。

公开(公告)号：US08339893B2

公开(公告)日：2012-12-25

申请号：US12566862

申请日：2009-09-25

申请人： Yuen H. Chan ,  Louis C. Hsu ,  Xu Ouyang ,  Robert C. Wong

发明人： Yuen H. Chan ,  Louis C. Hsu ,  Xu Ouyang ,  Robert C. Wong

IPC分类号： G11C8/00

CPC分类号： G11C8/16 ,  G11C11/412

摘要： A static random access memory (SRAM) cell includes a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio. A static random access memory (SRAM) array includes a plurality of SRAM cells, an SRAM cell including a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio.

摘要翻译： 静态随机存取存储器（SRAM）单元包括第一读取端口，第一读取端口具有第一β比率; 和写入端口，所述写入端口具有基本上低于所述第一β比率的第二β比率。 静态随机存取存储器（SRAM）阵列包括多个SRAM单元，包括第一读取端口的SRAM单元，第一读取端口具有第一β比率; 和写入端口，所述写入端口具有基本上低于所述第一β比率的第二β比率。

公开(公告)号：US20120184076A1

公开(公告)日：2012-07-19

申请号：US13429556

申请日：2012-03-26

申请人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

发明人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/7881

摘要： A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.

摘要翻译： 具有增强的电容耦合系数比（CCCR）的闪速存储器结构可以以自对准方式制造，同时使用半导体衬底，该半导体衬底具有相对于围绕有源区域的隔离区域在孔内凹入的有源区域 。 闪速存储器结构包括不在隔离区上方升起的浮栅，并且优选地由具有U形的单层组成。 U形有助于增强电容耦合系数比。

公开(公告)号：US08009461B2

公开(公告)日：2011-08-30

申请号：US11969981

申请日：2008-01-07

申请人： Xu Ouyang ,  Louis C. Hsu

发明人： Xu Ouyang ,  Louis C. Hsu

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： A semiconductor device includes a SRAM having a pair of MCSFETs connected as access transistors (pass gates). A design structure embodied or stored in a machine readable medium includes a SRAM having two MCSFETs connected as access transistors.

摘要翻译： 半导体器件包括具有连接作为存取晶体管（通孔）的一对MCSFET的SRAM。 体现或存储在机器可读介质中的设计结构包括具有连接作为存取晶体管的两个MCSFET的SRAM。

公开(公告)号：US08193575B2

公开(公告)日：2012-06-05

申请号：US12027496

申请日：2008-02-07

申请人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

发明人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/7881

摘要： A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.

摘要翻译： 具有增强的电容耦合系数比（CCCR）的闪速存储器结构可以以自对准方式制造，同时使用半导体衬底，该半导体衬底具有相对于围绕有源区域的隔离区域在孔内凹入的有源区域 。 闪速存储器结构包括不在隔离区上方升起的浮栅，并且优选地由具有U形的单层组成。 U形有助于增强电容耦合系数比。