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公开(公告)号：US5276862A
公开(公告)日：1994-01-04
申请号：US682801
申请日：1991-04-09
申请人： Lowell D. McCulley , Russell W. Guenthner , Clinton B. Eckard , Leonard Rabins , William A. Shelly , Ronald E. Lange , David S. Edwards
发明人： Lowell D. McCulley , Russell W. Guenthner , Clinton B. Eckard , Leonard Rabins , William A. Shelly , Ronald E. Lange , David S. Edwards
CPC分类号： G06F11/1441 , G06F11/1641 , G06F11/1637
摘要： In order to gather, store temporarily and deliver (if needed) central processor safestore information, a multiphase clock is employed to capture (one full clock cycle behind) the safestore information which typically includes all software visible registers in all (or selected) data manipulation chips of the CPU by routing the safestore information through temporary storage (under the influence of the multiphase clock) in a cache data array and into a special purpose XRAM module. Thus, upon the sensing of a fault, valid safestore information is available in the XRAM for analysis and, if appropriate, resumption of operation at a sequential point just previous to that at which the fault occurred.
摘要翻译： 为了收集，存储和交付（如果需要的话）中央处理器保险箱信息，采用多相时钟来捕获（一个完整的时钟周期）保存存储信息，这些信息通常包括所有（或选定的）数据操作中的所有软件可见寄存器 通过临时存储（在多相时钟的影响下）将缓存存储信息路由到高速缓存数据阵列中并进入特殊目的XRAM模块，从而使CPU的芯片。 因此，在检测到故障时，XRAM中有效的保险箱信息可用于分析，如果适用，在刚刚发生故障的连续点恢复运行。
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2.发明授权Equal access to prevent gateword dominance in a multiprocessor write-into-cache environment 有权在多处理器写入高速缓存环境中等同的访问来防止门字优势公开(公告)号：US06970977B2
公开(公告)日：2005-11-29
申请号：US10403703
申请日：2003-03-31
CPC分类号： G06F12/084
摘要： In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data. When the given processor completes use of the common code/data, it writes the gateword OPEN in its private cache, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword OPEN in memory.
摘要翻译： 一种多处理器写入高速缓存数据处理系统，包括：存储器; 至少第一和第二共享高速缓存; 耦合存储器和共享缓存的系统总线; 至少一个处理器具有分别耦合到每个共享高速缓存的专用高速缓存; 方法和装置，用于防止存储在存储器中的门字的所有权，其控制对在处理器中运行的进程共享的共同代码/数据的访问，通过该处理器，由给定处理器通过执行连续的交换操作来获得门字的读取副本 内存和给定处理器的共享缓存，以及给定的处理器的共享缓存和专用缓存。 如果门字被发现是OPEN，则由给定的处理器关闭，并且在给定处理器的专用高速缓存和共享高速缓存之间执行连续的交换操作，并且共享高速缓存和存储器将门字CLOSEd写入存储器，使得给定的处理器获得 独占访问受管制的通用代码/数据。 当给定的处理器完成使用通用代码/数据时，它将门字OPEN写入其专用缓存，并且在给定处理器的专用高速缓存和共享高速缓存之间执行连续的交换操作，共享高速缓存和存储器将门槛OPEN写入存储器 。
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3.发明授权
公开(公告)号：US5894581A
公开(公告)日：1999-04-13
申请号：US48339
申请日：1993-04-15
摘要： In order to reduce the size of the memory employed to store firmware, the firmware is written in virtual control words which are then reduced by allotting them to a primary control word memory and at least one secondary control word memory which is addressed by a field in the primary control word memory. A virtual set of secondary control words are each divided into a plurality of fields, and each field of each secondary virtual control word is marked as guarded or "don't care". If a field is marked as "don't care", the function represented by the virtual control word will perform properly no matter what the content of that field. Virtual control word pairs are then examined to ascertain if they can be combined into a single control word. If the guarded fields in the first virtual control word align with the "don't care" fields in the second virtual control word and vice versa, the two virtual control words can be combined into a single control word containing the contents of the guarded fields from both virtual control words, the remaining fields, if any, remaining "don't care". This process may be reiterated to determine if the combined control word can be further combined with another virtual control word. In operation, all the functions represented by a combined control word are executed by calling for that single control word stored in the secondary control word memory.
摘要翻译： 为了减小用于存储固件的存储器的大小，固件被写入虚拟控制字中，然后通过将固件分配给主控制字存储器和至少一个辅助控制字存储器进行减少，该副控制字存储器由字段 主要控制字记忆。 一组辅助控制字分别分成多个字段，每个次要虚拟控制字的每个字段被标记为被保护的或“无关紧要”。 如果一个字段被标记为“不在乎”，虚拟控制字表示的功能将会正常执行，无论该字段的内容如何。 然后检查虚拟控制字对，以确定它们是否可以组合成单个控制字。 如果第一虚拟控制字中的保护字段与第二虚拟控制字中的“无关心”字段对齐，反之亦然，则两个虚拟控制字可以组合成包含被保护字段的内容的单个控制字 从两个虚拟控制词，其余的字段，如果有的话，剩下的“不关心”。 可以重申该过程以确定组合的控制字是否可以与另一个虚拟控制字进一步组合。 在操作中，通过调用存储在辅助控制字存储器中的单个控制字来执行由组合控制字表示的所有功能。
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公开(公告)号：US5862308A
公开(公告)日：1999-01-19
申请号：US869787
申请日：1997-06-05
CPC分类号： G06F11/0724 , G06F11/0793
摘要： A fault handling process in a computer system subject to CPU design errors and functioning under an operating system (OS) having an integral fault handling module includes the steps of: setting an intercept flag when a central processor fault occurs if the fault is to be directed to a preprocessor; establishing a safestore frame which includes information identifying the type of fault and whether the intercept flag is set; and transferring control to the OS fault handling module; then in the OS fault handling module, determining whether the intercept flag is set; if the intercept flag is not set, handling the fault in the OS fault module; if the intercept flag is set, transferring control from the OS fault module to an Intercept Process written in machine language; and handling the fault in the Intercept Process. This renders the resolution of faults due to correctable CPU design errors independent of the OS employed at a given installation and customizable to a given system without the need to revise the OS fault modules for each OS. As each such design error is worked out (e.g., by installing a substitute integrated circuit in which the error has been corrected), the Intercept Process (and CPU firmware) can be modified to remove monitoring and handling for faults due to the corrected error.
摘要翻译： 在具有整体故障处理模块的操作系统（OS）下遭受CPU设计错误和功能的计算机系统中的故障处理过程包括以下步骤：当故障要被引导时发生中央处理器故障时设置拦截标志 到预处理器 建立一个保险箱框架，其中包括识别故障类型的信息以及是否设置了拦截标志; 并将控制转移到OS故障处理模块; 然后在OS故障处理模块中，确定是否设置了拦截标志; 如果拦截标志未设置，则处理OS故障模块中的故障; 如果设置了拦截标志，则将控制从OS故障模块传送到以机器语言编写的拦截过程; 并处理拦截过程中的故障。 这使得由于可修正的CPU设计错误而导致的故障解决，独立于给定安装时使用的OS，并且可以自定义给给定的系统，而无需修改每个操作系统的操作系统故障模块。 由于每个这样的设计错误被解决（例如，通过安装错误已被校正的替换集成电路），可以修改截取过程（和CPU固件），以消除由于校正错误导致的故障的监视和处理。
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