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1.发明授权Method and apparatus for testing redundant word and bit lines in a memory array 失效用于测试存储器阵列中的冗余字和位线的方法和装置
公开(公告)号：US5631868A
公开(公告)日：1997-05-20
申请号：US563831
申请日：1995-11-28
CPC分类号： G11C29/838 , G11C29/24
摘要： A method and apparatus for evaluating a memory having memory elements and redundant memory elements for redundancy replacement. The redundant memory elements are tested to determine the number of good redundant memory elements. The memory elements are also tested to determine whether there are any failing memory elements. It is then determined whether a sufficient number of good redundant elements are available to replace the failing memory elements. If an insufficient number of redundant memory elements are available, the testing is stopped.
摘要翻译： 一种用于评估具有存储元件的存储器和用于冗余替换的冗余存储器元件的方法和装置。 测试冗余存储器元件以确定良好冗余存储器元件的数量。 还测试存储器元件以确定是否存在任何故障存储器元件。 然后确定足够数量的良好冗余元件是否可用于替换故障存储器元件。 如果冗余内存元素数量不足，则会停止测试。
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公开(公告)号：US5539753A
公开(公告)日：1996-07-23
申请号：US512688
申请日：1995-08-10
IPC分类号： G11C29/00 , G01R31/3185 , G06F11/273 , G11C29/12 , G06F11/00
CPC分类号： G06F11/2733 , G01R31/318516
摘要： A circuit, as a logic circuit or a memory circuit, having testing latches. The testing latches include an input latch, a slave latch, and true and complement output latches. The output of the slave latch is NANDed with a DESELECT signal to deselect the output latches. The testing latches can be used in a method of characterizing or testing a memory or logic integrated circuit with scannable output latches. At least one output latch has an input latch, a slave latch, and an output latch which may contain a Complement Latch, and a True latch. In the testing process an output of the slave latch is NANDed with a deselect signal to allow testing or characterization by masking known "fail" signals.
摘要翻译： 作为具有测试锁存器的逻辑电路或存储器电路的电路。 测试锁存器包括输入锁存器，从锁存器，以及真和补输出锁存器。 从锁存器的输出与DESELECT信号对准，以取消选择输出锁存器。 测试锁存器可以用于表征或测试具有可扫描输出锁存器的存储器或逻辑集成电路的方法。 至少一个输出锁存器具有输入锁存器，从锁存器和可包含补码锁存器和真锁存器的输出锁存器。 在测试过程中，从锁存器的输出与取消选择信号NAND通过屏蔽已知的“故障”信号进行测试或表征。
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