公开(公告)号：US06505328B1

公开(公告)日：2003-01-07

申请号：US09300540

申请日：1999-04-27

申请人： Lukas P. P. P. Van Ginneken ,  Patrick R. Groeneveld ,  Wilhelmus J. M. Philipsen

发明人： Lukas P. P. P. Van Ginneken ,  Patrick R. Groeneveld ,  Wilhelmus J. M. Philipsen

IPC分类号： G06F1750

CPC分类号： G06F17/505 ,  G06F17/5045 ,  G06F17/5068

摘要： An automated logic circuit design system uses a common database to store design data at different states of the design process, including data-flow graphs, netlists and layout descriptions. In this way, the need to translate circuit descriptions between tools is eliminated, thus leading to increased speed, flexibility and integration. The common database includes entities, models, cells, pins, busses and nets. The data-flow graphs are stored as graphs, the nodes in a graph as cells, and the edges as busses. Physical design data is available by storing the cells in a model in a KD tree. This allows queries on cells in the netlist located in the layout within arbitrary areas.

公开(公告)号：US06553338B1

公开(公告)日：2003-04-22

申请号：US09300557

申请日：1999-04-27

申请人： Premal V. Buch ,  Hamid Savoj ,  Lukas P. P. P. Van Ginneken

发明人： Premal V. Buch ,  Hamid Savoj ,  Lukas P. P. P. Van Ginneken

IPC分类号： G06F1750

CPC分类号： G06F17/505 ,  G06F17/5022

摘要： A strategy for optimal buffering in the case of an infinitely long wire buffered with an arbitrary number of equally spaced single-size buffers is presented. A simple but efficient technique is proposed using this to choose a buffer size and determine a good inter-buffering distance up front, thus enabling fast, efficient buffer insertion. The analysis also allows representing delays of long wires as a simple function of the length and buffer and wire widths. Based on this, a novel constant wire delay approach is proposed where the proposed wire delay model is used for fairly accurate prediction of wire delays early in the design process and these predictions are later met via buffer insertion and wire sizing.

摘要翻译： 提出了在任意数量的等间距单个缓冲器中缓冲的无限长的线的情况下的优化缓冲策略。 提出了一种简单而有效的技术，用于选择缓冲区大小，并确定前面的良好的缓冲间距离，从而实现快速，高效的缓冲区插入。 该分析还允许将长线的延迟表示为长度和缓冲器和线宽的简单函数。 基于此，提出了一种新颖的恒定线延迟方法，其中提出的线延迟模型用于在设计过程的早期对线延迟进行相当准确的预测，并且这些预测稍后通过缓冲器插入和线尺寸来满足。