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公开(公告)号：US08724401B2
公开(公告)日：2014-05-13
申请号：US12568729
申请日：2009-09-29
申请人： Luke William Friendshuh , Mark Allen Gaertner , Jonathan Williams Haines , Timothy Richard Feldman
发明人： Luke William Friendshuh , Mark Allen Gaertner , Jonathan Williams Haines , Timothy Richard Feldman
摘要： Data stripes and addressing for flash memory devices are provided. Flash memory devices illustratively have a plurality of programmable devices that are capable of simultaneously storing data. A plurality of erasure blocks are within each of the programmable devices, and each erasure block has pages of transistors. The flash memory devices are logically organized as a plurality of stripes. Each stripe has a height and a width. In an embodiment, the stripe height is greater than one page. In another embodiment, the stripe width is less than all of the programmable devices within the flash memory device.
摘要翻译： 提供闪存设备的数据条带和寻址。 闪存器件说明性地具有能够同时存储数据的多个可编程器件。 多个擦除块位于每个可编程器件内，并且每个擦除块具有晶体管页面。 闪存器件在逻辑上被组织成多个条纹。 每个条纹都有一个高度和一个宽度。 在一个实施例中，条带高度大于一页。 在另一个实施例中，条宽度小于闪存器件内的所有可编程器件。
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公开(公告)号：US20110075490A1
公开(公告)日：2011-03-31
申请号：US12568729
申请日：2009-09-29
申请人： Luke William Friendshuh , Mark Allen Gaertner , Jonathan Williams Haines , Timothy Richard Feldman
发明人： Luke William Friendshuh , Mark Allen Gaertner , Jonathan Williams Haines , Timothy Richard Feldman
摘要： Data stripes and addressing for flash memory devices are provided. Flash memory devices illustratively have a plurality of programmable devices that are capable of simultaneously storing data. A plurality of erasure blocks are within each of the programmable devices, and each erasure block has pages of transistors. The flash memory devices are logically organized as a plurality of stripes. Each stripe has a height and a width. In an embodiment, the stripe height is greater than one page. In another embodiment, the stripe width is less than all of the programmable devices within the flash memory device.
摘要翻译： 提供闪存设备的数据条带和寻址。 闪存器件说明性地具有能够同时存储数据的多个可编程器件。 多个擦除块位于每个可编程器件内，并且每个擦除块具有晶体管页面。 闪存器件在逻辑上被组织成多个条纹。 每个条纹都有一个高度和一个宽度。 在一个实施例中，条带高度大于一页。 在另一个实施例中，条宽度小于闪存器件内的所有可编程器件。
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公开(公告)号：US08560770B2
公开(公告)日：2013-10-15
申请号：US12618268
申请日：2009-11-13
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7203
摘要： The present disclosure provides a data storage system. In one example, the data storage system includes a data storage media component having a plurality of data storage locations. A first set of the plurality of data storage locations are allocated for a main data storage area. The data storage system also includes a controller configured to define a write cache for the main data storage area by selectively allocating a second set of the plurality of data storage locations.
摘要翻译： 本公开提供了一种数据存储系统。 在一个示例中，数据存储系统包括具有多个数据存储位置的数据存储介质组件。 为主数据存储区域分配多个数据存储位置的第一组。 数据存储系统还包括控制器，其被配置为通过选择性地分配多个数据存储位置的第二组来定义主数据存储区域的写高速缓存。
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公开(公告)号：US20110119442A1
公开(公告)日：2011-05-19
申请号：US12618268
申请日：2009-11-13
CPC分类号： G06F12/0246 , G06F2212/7203
摘要： The present disclosure provides a data storage system. In one example, the data storage system includes a data storage media component having a plurality of data storage locations. A first set of the plurality of data storage locations are allocated for a main data storage area. The data storage system also includes a controller configured to define a write cache for the main data storage area by selectively allocating a second set of the plurality of data storage locations.
摘要翻译： 本公开提供了一种数据存储系统。 在一个示例中，数据存储系统包括具有多个数据存储位置的数据存储介质组件。 为主数据存储区域分配多个数据存储位置的第一组。 数据存储系统还包括控制器，其被配置为通过选择性地分配多个数据存储位置的第二组来定义主数据存储区域的写高速缓存。
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公开(公告)号：US09104578B2
公开(公告)日：2015-08-11
申请号：US13543036
申请日：2012-07-06
申请人： James David Sawin , Luke William Friendshuh , Sumanth Jannyavula Venkata , Ryan James Goss , Mark Allen Gaertner
发明人： James David Sawin , Luke William Friendshuh , Sumanth Jannyavula Venkata , Ryan James Goss , Mark Allen Gaertner
CPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0895
摘要： A host read request affects a request address range of a main storage. A speculative address range proximate to the request address range is defined. Speculative data stored in the speculative address range is not requested via the host read request. A criterion is determined that is indicative of future read requests of associated with the speculative data. The speculative data is copied from the main storage to at least one of a non-volatile cache and a volatile cache together with data of the host read request in response to the criterion meeting a threshold. The non-volatile cache and the volatile cache mirror respective portions of the main storage.
摘要翻译： 主机读取请求影响主存储器的请求地址范围。 定义了接近请求地址范围的推测地址范围。 存储在推测地址范围内的推测数据不是通过主机读取请求来请求的。 确定指示与推测数据相关联的未来读取请求的标准。 响应于满足阈值的标准，将推测数据从主存储复制到非易失性高速缓存和易失性高速缓存以及主机读取请求的数据中的至少一个。 非易失性缓存和易失性高速缓存镜像主存储器的各个部分。
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