公开(公告)号：US20250053523A1

公开(公告)日：2025-02-13

申请号：US18932094

申请日：2024-10-30

Applicant: Lutron Technology Company LLC

Inventor： Andrew Karl Cooney ,  Devin N. Malanaphy ,  Matthew J. Price ,  Scott E. Shaw ,  Derek Thrasher

IPC: G06F13/16 ,  G06F13/24 ,  G06F13/28

Abstract: A control device may include a processor may include a core, a timer peripheral, and a peripheral direct memory access controller. The processor may include a receive port coupled to a communication port of the reporting device via a communication line. The control device may include a timer peripheral that can generate an enable signal and a timing signal, and a buffer circuit that may include an enable port for the enable signal for enabling/disabling the buffer circuit, an input port for the timing signal, and an output port coupled to the communication line. The processor may enable/disable the buffer circuit to control the timing of data bit(s) transmission across the communication line by the reporting device. The peripheral direct memory access controller may store the data bit(s) in a receive buffer during the bit period, and the core may subsequently retrieve the data bit(s) from the receiver buffer.

公开(公告)号：US12158850B2

公开(公告)日：2024-12-03

申请号：US17971138

申请日：2022-10-21

Applicant: Lutron Technology Company LLC

Inventor： Andrew Karl Cooney ,  Devin N. Malanaphy ,  Matthew J. Price ,  Scott E. Shaw ,  Derek Thrasher

IPC: G06F13/16 ,  G06F13/24 ,  G06F13/28 ,  G06F13/42

Abstract: A control device may include a processor may include a core, a timer peripheral, and a peripheral direct memory access controller. The processor may include a receive port coupled to a communication port of the reporting device via a communication line. The control device may include a timer peripheral that can generate an enable signal and a timing signal, and a buffer circuit that may include an enable port for the enable signal for enabling/disabling the buffer circuit, an input port for the timing signal, and an output port coupled to the communication line. The processor may enable/disable the buffer circuit to control the timing of data bit(s) transmission across the communication line by the reporting device. The peripheral direct memory access controller may store the data bit(s) in a receive buffer during the bit period, and the core may subsequently retrieve the data bit(s) from the receiver buffer.

公开(公告)号：US20230126727A1

公开(公告)日：2023-04-27

申请号：US17971138

申请日：2022-10-21

Applicant: Lutron Technology Company LLC

Inventor： Andrew Karl Cooney ,  Devin N. Malanaphy ,  Matthew J. Price ,  Scott E. Shaw ,  Derek Thrasher

IPC: G06F13/16 ,  G06F13/24 ,  G06F13/28

Abstract: A control device may include a processor may include a core, a timer peripheral, and a peripheral direct memory access controller. The processor may include a receive port coupled to a communication port of the reporting device via a communication line. The control device may include a timer peripheral that can generate an enable signal and a timing signal, and a buffer circuit that may include an enable port for the enable signal for enabling/disabling the buffer circuit, an input port for the timing signal, and an output port coupled to the communication line. The processor may enable/disable the buffer circuit to control the timing of data bit(s) transmission across the communication line by the reporting device. The peripheral direct memory access controller may store the data bit(s) in a receive buffer during the bit period, and the core may subsequently retrieve the data bit(s) from the receiver buffer.