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1.发明申请公开(公告)号：US20080159297A1
公开(公告)日：2008-07-03
申请号：US12044994
申请日：2008-03-09
IPC分类号： H04L12/56
CPC分类号： H04L47/50 , H04L2012/5679
摘要： A method and apparatus are provided for implementing hierarchical scheduling of oversubscribed virtual paths with underutilized bandwidth that works for both ATM (cell) and IP (frame) scheduling. A scheduler includes a first calendar for pipes and autonomous flows and a second calendar for pipe flows. A winner of a pipe or an autonomous flow is identified from the first calendar. Responsive to an identified winner pipe, a pipe queue is checked for an associated pipe flow for the winner pipe. Responsive to identifying an empty pipe queue for the winner pipe, a pipe win credit is assigned to the pipe without reattaching the winner pipe to the first calendar. Then a next winner is identified from the first calendar. When a winner pipe flow is identified from the second calendar and the pipe win credit is assigned to the pipe for the winner pipe flow, then the winner pipe flow is serviced without delay.
摘要翻译： 提供了一种方法和装置，用于实现对于ATM（小区）和IP（帧）调度工作的未充分利用的带宽的超额预订虚拟路径的分层调度。 调度器包括用于管道和自主流的第一日历和用于管道流的第二日历。 从第一个日历识别管道或自主流的获胜者。 对于确定的胜利者管道，检查管道队列以获得胜利管道的相关管道流量。 响应于为胜利者管道识别空管道队列，将管道赢取信用额度分配给管道，而不将胜利者管道重新连接到第一个日历。 然后从第一个日历识别下一个赢家。 当从第二个日历识别获胜者管道流量，并且将管道信贷分配给胜利者管道的管道时，优胜者管道流程将被无延误地维护。
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2.发明授权Method and apparatus for hierarchial scheduling of virtual paths with underutilized bandwidth 有权具有未充分利用带宽的虚拟路径的层次调度的方法和装置公开(公告)号：US07362706B2
公开(公告)日：2008-04-22
申请号：US10317413
申请日：2002-12-12
IPC分类号： H04L12/26
CPC分类号： H04L47/50 , H04L2012/5679
摘要： A method and apparatus are provided for implementing hierarchical scheduling of oversubscribed virtual paths with underutilized bandwidth that works for both ATM (cell) and IP (frame) scheduling. A scheduler includes a first calendar for pipes and autonomous flows and a second calendar for pipe flows. A winner of a pipe or an autonomous flow is identified from the first calendar. Responsive to an identified winner pipe, a pipe queue is checked for an associated pipe flow for the winner pipe. Responsive to identifying an empty pipe queue for the winner pipe, a pipe win credit is assigned to the pipe without reattaching the winner pipe to the first calendar. Then a next winner is identified from the first calendar. When a winner pipe flow is identified from the second calendar and the pipe win credit is assigned to the pipe for the winner pipe flow, then the winner pipe flow is serviced without delay.
摘要翻译： 提供了一种方法和装置，用于实现对于ATM（小区）和IP（帧）调度工作的未充分利用的带宽的超额预订的虚拟路径的分级调度。 调度器包括用于管道和自主流的第一日历和用于管道流的第二日历。 从第一个日历识别管道或自主流的获胜者。 对于确定的胜利者管道，检查管道队列以获得胜利管道的相关管道流量。 响应于为胜利者管道识别空管道队列，将管道赢取信用额度分配给管道，而不将胜利者管道重新连接到第一个日历。 然后从第一个日历识别下一个赢家。 当从第二个日历识别获胜者管道流量，并且将管道信贷分配给胜利者管道的管道时，优胜者管道流程将被无延误地维护。
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3.发明授权Method and apparatus for hierarchial scheduling of virtual paths with underutilized bandwidth 有权具有未充分利用带宽的虚拟路径的层次调度的方法和装置公开(公告)号：US07660251B2
公开(公告)日：2010-02-09
申请号：US12044994
申请日：2008-03-09
IPC分类号： H04L12/26
CPC分类号： H04L47/50 , H04L2012/5679
摘要： A method and apparatus are provided for implementing hierarchical scheduling of oversubscribed virtual paths with underutilized bandwidth that works for both ATM (cell) and IP (frame) scheduling. A scheduler includes a first calendar for pipes and autonomous flows and a second calendar for pipe flows. A winner of a pipe or an autonomous flow is identified from the first calendar. Responsive to an identified winner pipe, a pipe queue is checked for an associated pipe flow for the winner pipe. Responsive to identifying an empty pipe queue for the winner pipe, a pipe win credit is assigned to the pipe without reattaching the winner pipe to the first calendar. Then a next winner is identified from the first calendar. When a winner pipe flow is identified from the second calendar and the pipe win credit is assigned to the pipe for the winner pipe flow, then the winner pipe flow is serviced without delay.
摘要翻译： 提供了一种方法和装置，用于实现对于ATM（小区）和IP（帧）调度工作的未充分利用的带宽的超额预订虚拟路径的分层调度。 调度器包括用于管道和自主流的第一日历和用于管道流的第二日历。 从第一个日历识别管道或自主流的获胜者。 对于确定的胜利者管道，检查管道队列以获得胜利管道的相关管道流量。 响应于为胜利者管道识别空管道队列，将管道赢取信用额度分配给管道，而不将胜利者管道重新连接到第一个日历。 然后从第一个日历识别下一个赢家。 当从第二个日历识别获胜者管道流量，并且将管道信贷分配给胜利者管道的管道时，优胜者管道流程将被无延误地维护。
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公开(公告)号：US5649177A
公开(公告)日：1997-07-15
申请号：US563561
申请日：1995-11-28
CPC分类号： G06F1/12
摘要： The ability to harmonize the activities of individual computer system components with control signals is key to the operation of any computer system. Examples of this need for control include the need to write data to multiple registers on the same clock cycle, the need to clear values on multiple entities on the same clock cycle, and the need to stop and start the master clock pulse train itself. In the past, providing this control was not a problem because control signals could be reliably sent to all the timing dependent components within a single cycle of the master clock pulse train. This control methodology is called "single cycle control." Today, however, single cycle control is not trustworthy in all situations. Master clock pulse trains are so fast that single cycle control is no longer reliable when timing dependent components reside in locations distant from the control signal generating circuitry. The present invention provides reliable control in all cases, including the situation where a master clock pulse train is so fast that single cycle control is not viable.
摘要翻译： 将个人计算机系统组件的活动与控制信号协调一致的能力是任何计算机系统的运行的关键。 这种控制需求的例子包括需要在相同的时钟周期将数据写入多个寄存器，需要在同一时钟周期内清除多个实体上的值，以及需要停止和启动主时钟脉冲序列本身。 在过去，提供这种控制并不是问题，因为控制信号可以被可靠地发送到主时钟脉冲串的单个周期内的所有定时相关分量。 这种控制方法被称为“单循环控制”。 然而，今天，在所有情况下，单循环控制是不可靠的。 主时钟脉冲串非常快，当定时相关组件驻留在远离控制信号发生电路的位置时，单周期控制不再可靠。 本发明在所有情况下提供可靠的控制，包括主时钟脉冲串如此快以致单周期控制不可行的情况。
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5.发明授权Programmable oscillators for high frequency clock generation for simulation environments 失效用于模拟环境的高频时钟生成的可编程振荡器公开(公告)号：US07567137B2
公开(公告)日：2009-07-28
申请号：US11952613
申请日：2007-12-07
CPC分类号： G06F17/5045
摘要： A method and programmable oscillator model are provided for implementing high frequency clock generation for a simulation environment. The programmable oscillator model includes an internal ring oscillator for generating a high frequency clock. The internal ring oscillator counts a number of clocks and determines when to switch the reference clock. For example, a clock edge time is recorded as a two-byte field, where a high byte records a programmable number of fast clocks per clock edge, and a low byte records a fraction of a clock edge. Each time the reference clock switches a count down counter is loaded with the high byte, and the low byte is added to the current fraction. If the fraction has a carry, an additional fast clock is added to the count down counter.
摘要翻译： 提供了一种用于为模拟环境实现高频时钟生成的方法和可编程振荡器模型。 可编程振荡器模型包括用于产生高频时钟的内部环形振荡器。 内部振荡振荡器对多个时钟进行计数，并确定何时切换参考时钟。 例如，时钟边沿时间被记录为双字节字段，其中高字节记录每个时钟边沿的可编程数量的快速时钟，低字节记录时钟沿的一小部分。 每次参考时钟切换倒数计数器都加载高字节，低字节加到当前分数。 如果分数具有进位，则向递减计数器添加额外的快速时钟。
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6.发明授权Programmable oscillators for high frequency clock generation for simulation environments 失效用于模拟环境的高频时钟生成的可编程振荡器公开(公告)号：US07319367B2
公开(公告)日：2008-01-15
申请号：US11344903
申请日：2006-02-01
CPC分类号： G06F17/5045
摘要： A method and programmable oscillator model are provided for implementing high frequency clock generation for a simulation environment. The programmable oscillator model includes an internal ring oscillator for generating a high frequency clock. The internal ring oscillator counts a number of clocks and determines when to switch the reference clock. For example, a clock edge time is recorded as a two-byte field, where a high byte records a programmable number of fast clocks per clock edge, and a low byte records a fraction of a clock edge. Each time the reference clock switches a count down counter is loaded with the high byte, and the low byte is added to the current fraction. If the fraction has a carry, an additional fast clock is added to the count down counter.
摘要翻译： 提供了一种用于为模拟环境实现高频时钟生成的方法和可编程振荡器模型。 可编程振荡器模型包括用于产生高频时钟的内部环形振荡器。 内部振荡振荡器对多个时钟进行计数，并确定何时切换参考时钟。 例如，时钟边沿时间被记录为双字节字段，其中高字节记录每个时钟边沿的可编程数量的快速时钟，低字节记录时钟沿的一小部分。 每次参考时钟切换倒数计数器都加载高字节，低字节加到当前分数。 如果分数具有进位，则向递减计数器添加额外的快速时钟。
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公开(公告)号：US06523080B1
公开(公告)日：2003-02-18
申请号：US09014090
申请日：1998-01-27
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
IPC分类号： G06F1342
CPC分类号： G06F13/385
摘要： A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.
摘要翻译： 提供共享总线非顺序数据排序方法和装置。 识别最大总线宽度值和最小传输值。 响应于所识别的最大总线宽度值和最小传输值来识别最小数量的子传送。 具有用于接收和/或发送数据的最大数量的码片的总线单元在多个子传送期间以预定义的顺序接收数据。 在每个数据子传送期间，相应的预定义字被传送到总线单元的每个芯片。
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公开(公告)号：US5751990A
公开(公告)日：1998-05-12
申请号：US233654
申请日：1994-04-26
CPC分类号： G06F12/1063
摘要： A hierarchical memory utilizes a translation lookaside buffer for rapid recovery of virtual to real address mappings and a cache system. Lines in the cache are identified in the cache directory by pointers to entries in the translation lookaside buffer. This eliminates redundant listings of the virtual and real addresses for the cache line from the cache directory allowing the directory to be small in size. Upon a memory access by a processing unit, a cache hash address is generated to access a translation lookaside buffer entry allowing comparison of the address stored in the TLB entry with the address of the memory access. Congruence implies a hit. Concurrently, the cache hash address indicates a pointer from the cache directory. The pointer should correspond to the cache hash address to indicate a cache directory hit. Where both occur a cache hit has occurred.
摘要翻译： 分层存储器利用翻译后备缓冲器来快速恢复虚拟到真实的地址映射和缓存系统。 缓存中的行通过指向转换后备缓冲区中的条目的缓存目录中标识。 这消除了缓存目录中虚拟和实际地址的高速缓存行的冗余清单，允许目录体积小。 在由处理单元进行存储器访问时，生成高速缓存散列地址以访问转换后备缓冲器条目，允许将存储在TLB条目中的地址与存储器访问的地址进行比较。 一致意味着一击。 同时，缓存散列地址指示缓存目录中的指针。 指针应对应于缓存哈希地址，以指示缓存目录命中。 发生高速缓存命中的地方。
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公开(公告)号：US5748919A
公开(公告)日：1998-05-05
申请号：US677775
申请日：1996-07-10
申请人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
发明人： Herman Lee Blackmon , Robert Allen Drehmel , Lyle Edwin Grosbach , Kent Harold Haselhorst , David John Krolak , James Anthony Marcella , Peder James Paulson
CPC分类号： G06F13/4018
摘要： A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.
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