公开(公告)号：US20230033998A1

公开(公告)日：2023-02-02

申请号：US17539257

申请日：2021-12-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Bo-Rong LIN ,  Ming-Liang WEI ,  Hsiang-Pang LI ,  Nai-Jia DONG ,  Hsiang-Yun CHENG ,  Chia-Lin YANG

IPC: G06F12/0804

Abstract: A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.

公开(公告)号：US20220334757A1

公开(公告)日：2022-10-20

申请号：US17403927

申请日：2021-08-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Chun LI ,  Han-Wen HU ,  Bo-Rong LIN ,  Huai-Mu WANG

IPC: G06F3/06

Abstract: A storage device and a data accessing method are disclosed, wherein the storage device includes a memory circuit and a control circuit. The memory circuit includes a plurality of multi-level cells, and each of the multi-level cells is configured to store at least a first bit, a second bit and a third bit in at least a first page, a second page and a third page. The control circuit is configured to read the first bits according to a one-time reading operation related to the first bits, read the second bits according to M-times reading operations related to the second bits, and read the third bits according to N-times reading operations related to the third bits, wherein the difference between M and N is less than or equal to one.

公开(公告)号：US20220334964A1

公开(公告)日：2022-10-20

申请号：US17542557

申请日：2021-12-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Wen HU ,  Yung-Chun LI ,  Bo-Rong LIN ,  Huai-Mu WANG

IPC: G06F12/0802

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a plurality of page buffers, storing an input data; a plurality of memory planes coupled to the page buffers, based on received addresses of the memory planes, a plurality of weights stored in the memory planes, the memory planes performing bit multiplication on the weights and the input data in the page buffers in parallel to generate a plurality of bit multiplication results in parallel, the bit multiplication results stored back to the page buffers; and at least one accumulation circuit coupled to the page buffers, for performing bit accumulation on the bit multiplication results of the memory planes in parallel or in sequential to generate a multiply-accumulate (MAC) operation result.

公开(公告)号：US20220075600A1

公开(公告)日：2022-03-10

申请号：US17375024

申请日：2021-07-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Wen HU ,  Yung-Chun LEE ,  Bo-Rong LIN ,  Huai-Mu WANG

IPC: G06F7/544 ,  G06F7/527 ,  H03M1/36 ,  H03M1/14

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results, wherein in performing bitwise multiplication, the memory cells generate a plurality of memory cell currents; a digital accumulating circuit for performing a digital accumulating on the multiplication results; an analog accumulating circuit for performing an analog accumulating on the memory cell currents to generate a first MAC operation result; and a decision unit for deciding whether to perform the analog accumulating; the digital accumulating or a hybrid accumulating, wherein in performing the hybrid accumulating, whether the digital accumulating circuit is triggered is based on the first MAC operation result.

公开(公告)号：US20250157508A1

公开(公告)日：2025-05-15

申请号：US18641578

申请日：2024-04-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Huai-Mu WANG ,  Han-Wen HU ,  Yung-Chun LI ,  Bo-Rong LIN

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/16

Abstract: The application discloses a memory device and a computation method thereof. A plurality of weight data are stored in a plurality of first memory cells of the memory device. A plurality of input data are input via a plurality of string select lines. A plurality of memory cell currents are generated in the plurality of first memory cells based on the weight data and the input data. The memory cell currents are summed on a plurality of bit lines coupled to the plurality of string select lines to obtain a plurality of summed currents. The summed currents are converted into a plurality of analog-to-digital conversion results. The plurality of analog-to-digital conversion results are accumulated to obtain a computational result.

公开(公告)号：US20220075599A1

公开(公告)日：2022-03-10

申请号：US17365034

申请日：2021-07-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Wen HU ,  Yung-Chun LEE ,  Bo-Rong LIN ,  Huai-Mu WANG

IPC: G06F7/544 ,  G11C7/06

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit coupled to the memory array, for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results; a counting unit coupled to the multiplication circuit, for performing bitwise counting on the multiplication results to generate a MAC (multiplication and accumulation) operation result.