公开(公告)号：US20250157548A1

公开(公告)日：2025-05-15

申请号：US18610368

申请日：2024-03-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Huai-Mu WANG ,  Han-Wen HU ,  Yung-Chun LI ,  Chih-Chang HSIEH ,  Shang-Ting LIN

IPC: G11C16/26 ,  G11C16/04

Abstract: The disclosure discloses a memory device and an operation method thereof. A target memory cell and at least one replicated memory cell belonging to the same memory string are selected. A target weight value written into the target memory cell is replicated to the at least one replicated memory cell, wherein the target memory cell and the at least one replicated memory cell store the target weight value. In response to a command of reading or computing on the target memory cell received by the memory device, reading or computing is performed on the target memory cell and the at least one replicated memory cell simultaneously.

公开(公告)号：US20200264790A1

公开(公告)日：2020-08-20

申请号：US16279494

申请日：2019-02-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng CHANG ,  Han-Wen HU

IPC: G06F3/06 ,  G06F7/544 ,  G06N3/02

Abstract: A memory device includes an array of composite memory units. At least one of the composite memory units comprises a first memory cell of a first type, a second memory cell of a second type, a first intra-unit data path connecting the first memory cell to the second memory cell, and a first data path control switch. The first data path control switch is responsive to a data transfer enable signal which enables data transfer between the first memory cell and the second memory cell through the first intra-unit data path.

公开(公告)号：US20230298660A1

公开(公告)日：2023-09-21

申请号：US17694771

申请日：2022-03-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Wen HU

IPC: G11C11/4091 ,  G11C11/4099 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C11/4099 ,  G11C11/4074 ,  G11C11/4096

Abstract: The application provides a sense amplifier and an operation method thereof. The operation method for the sense amplifier includes: during a first phase, initializing a first sensing input voltage and a second input sensing voltage; and recording a first sensing output voltage and a second sensing output voltage of a previous round by charges stored in a plurality of transistors of the sense amplifier; during a second phase, sampling the first sensing output voltage and the second sensing output voltage of a current round as a plurality of transit points; during a first sub-phase of a third phase, amplifying a voltage difference between an input signal and a first reference voltage; and during a second sub-phase of the third phase, pulling the first sensing output voltage and the second sensing output voltage into a full-swing voltage range, and recording charges to the transistors of the sense amplifier.

公开(公告)号：US20220334757A1

公开(公告)日：2022-10-20

申请号：US17403927

申请日：2021-08-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Chun LI ,  Han-Wen HU ,  Bo-Rong LIN ,  Huai-Mu WANG

IPC: G06F3/06

Abstract: A storage device and a data accessing method are disclosed, wherein the storage device includes a memory circuit and a control circuit. The memory circuit includes a plurality of multi-level cells, and each of the multi-level cells is configured to store at least a first bit, a second bit and a third bit in at least a first page, a second page and a third page. The control circuit is configured to read the first bits according to a one-time reading operation related to the first bits, read the second bits according to M-times reading operations related to the second bits, and read the third bits according to N-times reading operations related to the third bits, wherein the difference between M and N is less than or equal to one.

公开(公告)号：US20250157508A1

公开(公告)日：2025-05-15

申请号：US18641578

申请日：2024-04-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Huai-Mu WANG ,  Han-Wen HU ,  Yung-Chun LI ,  Bo-Rong LIN

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/16

Abstract: The application discloses a memory device and a computation method thereof. A plurality of weight data are stored in a plurality of first memory cells of the memory device. A plurality of input data are input via a plurality of string select lines. A plurality of memory cell currents are generated in the plurality of first memory cells based on the weight data and the input data. The memory cell currents are summed on a plurality of bit lines coupled to the plurality of string select lines to obtain a plurality of summed currents. The summed currents are converted into a plurality of analog-to-digital conversion results. The plurality of analog-to-digital conversion results are accumulated to obtain a computational result.

公开(公告)号：US20220075599A1

公开(公告)日：2022-03-10

申请号：US17365034

申请日：2021-07-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Wen HU ,  Yung-Chun LEE ,  Bo-Rong LIN ,  Huai-Mu WANG

IPC: G06F7/544 ,  G11C7/06

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit coupled to the memory array, for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results; a counting unit coupled to the multiplication circuit, for performing bitwise counting on the multiplication results to generate a MAC (multiplication and accumulation) operation result.

公开(公告)号：US20220334964A1

公开(公告)日：2022-10-20

申请号：US17542557

申请日：2021-12-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Wen HU ,  Yung-Chun LI ,  Bo-Rong LIN ,  Huai-Mu WANG

IPC: G06F12/0802

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a plurality of page buffers, storing an input data; a plurality of memory planes coupled to the page buffers, based on received addresses of the memory planes, a plurality of weights stored in the memory planes, the memory planes performing bit multiplication on the weights and the input data in the page buffers in parallel to generate a plurality of bit multiplication results in parallel, the bit multiplication results stored back to the page buffers; and at least one accumulation circuit coupled to the page buffers, for performing bit accumulation on the bit multiplication results of the memory planes in parallel or in sequential to generate a multiply-accumulate (MAC) operation result.

公开(公告)号：US20220075600A1

公开(公告)日：2022-03-10

申请号：US17375024

申请日：2021-07-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Wen HU ,  Yung-Chun LEE ,  Bo-Rong LIN ,  Huai-Mu WANG

IPC: G06F7/544 ,  G06F7/527 ,  H03M1/36 ,  H03M1/14

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results, wherein in performing bitwise multiplication, the memory cells generate a plurality of memory cell currents; a digital accumulating circuit for performing a digital accumulating on the multiplication results; an analog accumulating circuit for performing an analog accumulating on the memory cell currents to generate a first MAC operation result; and a decision unit for deciding whether to perform the analog accumulating; the digital accumulating or a hybrid accumulating, wherein in performing the hybrid accumulating, whether the digital accumulating circuit is triggered is based on the first MAC operation result.

公开(公告)号：US20250158628A1

公开(公告)日：2025-05-15

申请号：US18736681

申请日：2024-06-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Wen HU ,  Yung-Chun LI ,  Chih-Chang HSIEH ,  BO-RONG LIN ,  Huai-Mu WANG ,  Chih-Huai SHIH

IPC: H03M1/12 ,  H03M1/38 ,  H03M1/50

Abstract: An analog-to-digital conversion device, includes the following elements. A sensing circuit, coupled to a bit line of a memory array, and used to sense a current in the bit line to generate a bit-sequence, the bit-sequence has a form of a thermometer code to represent an analog value. A latch logic circuit, including a plurality of latches and a plurality of logic circuits to form a page buffer of the memory array, and used to generate a bit-set according to the bit-sequence, the bit-set has a form of a binary code to represent a digital value. The latches and the logic circuits are used to perform a conversion process to convert the bit-sequence into the bit-set, and the conversion process has a bit width.

公开(公告)号：US20250156420A1

公开(公告)日：2025-05-15

申请号：US18655472

申请日：2024-05-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Huai SHIH ,  Han-Wen HU ,  Huai-Mu WANG ,  Yung-Chun LI

IPC: G06F16/2455 ,  G06F16/28

Abstract: A filtered search method, for performing a search within a data set, and the data set includes several data points. The filtered search method includes the following steps. Dividing the data set into several clusters based on a similarity of the data points. Dividing each of the clusters into an inlier part and an outlier part based on a distribution density of the data points. Performing a coarse search on all of the inlier parts, to filter out inlier parts of a first candidate number. Performing a fine search on the inlier parts of the first candidate number, to search data points of a second candidate number. Obtaining a search result based on the data points of the second candidate number, and the data points of the second candidate number are close to a target point.