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    ENCODER, DECODER, ENCODING METHOD AND DECODING METHOD BASED ON LOW-DENSITY PARITY-CHECK CODE
    2.
    发明申请
    ENCODER, DECODER, ENCODING METHOD AND DECODING METHOD BASED ON LOW-DENSITY PARITY-CHECK CODE 有权

    公开(公告)号：US20210119645A1

    公开(公告)日：2021-04-22

    申请号：US16658191

    申请日：2019-10-21

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chih-Huai SHIH ,  Yu-Ming HUANG ,  Hsiang-Pang LI ,  Hsi-Chia CHANG

    IPC: H03M13/25 ,  H03M13/11 ,  H03M13/29 ,  H03M13/15

    Abstract: The present invention discloses an encoder, a decoder, an encoding method and a decoding method based on Low-Density Parity-Check (LDPC) code. The encoding method comprises: receiving, by an encoder, an information for encoding; generating, by the encoder, a first portion codeword according to a first encoding rule and the information for encoding, wherein the first encoding rule is an encoding rule configured to generate LDPC code; generating, by the encoder, a second portion codeword according to a second encoding rule different from the first encoding rule and a double check region of the first portion codeword; and concatenating, by the encoder, the first portion codeword and the second portion codeword to generate a codeword. A plurality of trapping sets corresponding to the first encoding rule include at least one error bit within the double check region.

    MEMORY SYSTEM FOR MAINTAINING DATA CONSISTENCY AND OPERATION METHOD THEREOF
    3.
    发明申请
    MEMORY SYSTEM FOR MAINTAINING DATA CONSISTENCY AND OPERATION METHOD THEREOF 有权

    公开(公告)号：US20230033998A1

    公开(公告)日：2023-02-02

    申请号：US17539257

    申请日：2021-12-01

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Bo-Rong LIN ,  Ming-Liang WEI ,  Hsiang-Pang LI ,  Nai-Jia DONG ,  Hsiang-Yun CHENG ,  Chia-Lin YANG

    IPC: G06F12/0804

    Abstract: A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.

    MEMORY SYSTEM WITH UNIFORM DECODER AND OPERATING METHOD OF SAME
    4.
    发明申请
    MEMORY SYSTEM WITH UNIFORM DECODER AND OPERATING METHOD OF SAME 有权
    具有均匀解码器的存储器系统及其操作方法

    公开(公告)号：US20170032826A1

    公开(公告)日：2017-02-02

    申请号：US14813759

    申请日：2015-07-30

    Applicant: Macronix International Co., Ltd.

    Inventor： Hsiang-Pang LI ,  Kin-Chu HO

    IPC: G11C7/06 ,  G11C7/10

    CPC classification number: G11C7/062 ,  G11C7/10 ,  G11C7/1006 ,  G11C16/26 ,  G11C2207/063 ,  G11C2207/068

    Abstract: A memory system includes a memory array including a plurality of memory cells, and an encoder operatively coupled to the memory array, for encoding an original data element to be programmed into the memory cells into a uniform data element in which the number of “0”s approximately equals the number of “1”s.

    Abstract translation: 存储器系统包括包括多个存储器单元的存储器阵列和可操作地耦合到存储器阵列的编码器，用于将要编程到存储器单元中的原始数据元件编码为统一数据元素，其中数量“0” 大约等于“1”的数量。

    STORAGE SYSTEM FOR PROCESSING GENOME SEQUENCES
    5.
    发明公开
    STORAGE SYSTEM FOR PROCESSING GENOME SEQUENCES 审中-公开

    公开(公告)号：US20240355390A1

    公开(公告)日：2024-10-24

    申请号：US18595672

    申请日：2024-03-05

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Ming-Liang WEI ,  Hsiang-Pang LI ,  You-Kai ZHENG ,  Chia-Lin YANG

    IPC: G11C13/02 ,  G16B30/10 ,  G16B50/30

    CPC classification number: G11C13/02 ,  G16B30/10 ,  G16B50/30

    Abstract: A storage system capable of executing data processing, includes the following elements. A first control unit of a storage device, for cooperating with a sequencer to perform a clustering process on a plurality of original sequences to obtain a plurality of read sequences, generating a plurality of read binary vectors corresponding to the read sequences, and generating a pruned filtering binary vector according to a reference sequence. A first storage module of the storage device, for storing the read binary vectors and the pruned filtering binary vector, and executing an in-memory computing (IMC) according to the read binary vectors and the pruned filtering binary vector, so as to generate a filtered cluster read set. A processing device, for executing an aligning process according to the filtered cluster read set and the reference sequence.

    MEMORY DEVICE AND OPERATING METHOD OF SAME
    7.
    发明申请
    MEMORY DEVICE AND OPERATING METHOD OF SAME 有权
    存储器件及其操作方法

    公开(公告)号：US20160299710A1

    公开(公告)日：2016-10-13

    申请号：US14683630

    申请日：2015-04-10

    Applicant: Macronix International Co., Ltd

    Inventor： Yu-Ming CHANG ,  Wei-Chieh HUANG ,  Li-Chun HUANG ,  Hung-Sheng CHANG ,  Hsiang-Pang LI ,  Ting-Yu LIU ,  Chien-Hsin LIU ,  Nai-Ping KUO

    IPC: G06F3/06 ,  G06F12/08

    CPC classification number: G06F3/0619 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0679 ,  G06F11/00 ,  G06F11/14 ,  G06F12/0246 ,  G06F12/0806 ,  G06F2212/621

    Abstract: A memory device includes a memory controller and a non-volatile memory communicatively coupled to the memory controller and storing a mapping table and a journal table. The memory controller is configured to write data and a logical address of the data into the non-volatile memory, load mapping information related to the logical address of the data from the mapping table of the non-volatile memory into a mapping cache of the memory controller, update the mapping cache with an updated mapping relationship between the logical address of the data and a physical address of the data, and perform a journaling operation to write the updated mapping relationship into the journal table.

    Abstract translation: 存储器设备包括通信地耦合到存储器控制器并存储映射表和日志表的存储器控​​制器和非易失性存储器。 存储器控制器被配置为将数据和逻辑地址写入到非易失性存储器中，将与数据的逻辑地址相关的映射信息从非易失性存储器的映射表加载到存储器的映射高速缓存中 控制器，使用数据的逻辑地址与数据的物理地址之间的更新的映射关系来更新映射高速缓存，并且执行日志操作以将更新的映射关系写入日志表。

    EXTENDED POLAR CODES
    8.
    发明申请
    EXTENDED POLAR CODES 审中-公开

    公开(公告)号：US20170222757A1

    公开(公告)日：2017-08-03

    申请号：US15287120

    申请日：2016-10-06

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Ming HUANG ,  Hsiang-Pang LI ,  Hsie-Chia CHANG

    IPC: H04L1/00 ,  H03M13/00 ,  H03M13/13

    CPC classification number: H04L1/0058 ,  H03M13/13 ,  H03M13/616 ,  H03M13/618 ,  H04L1/0041 ,  H04L1/0067

    Abstract: A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N−K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q−K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q−K frozen bits are allocated to the N−K frozen bit-channels and the q additional frozen bit-channels.

    LENGTH-COMPATIBLE EXTENDED POLAR CODES
    10.
    发明申请
    LENGTH-COMPATIBLE EXTENDED POLAR CODES 有权
    长期兼容扩展极性代码

    公开(公告)号：US20160294418A1

    公开(公告)日：2016-10-06

    申请号：US14794059

    申请日：2015-07-08

    Applicant: Macronix International Co., Ltd.

    Inventor： Yu-Ming HUANG ,  Hsiang-Pang LI ,  Hsie-Chia CHANG

    IPC: H03M13/13 ,  H04L1/00

    CPC classification number: H03M13/616 ,  H03M13/13 ,  H03M13/618 ,  H03M13/635 ,  H04L1/0057 ,  H04L1/0067

    Abstract: A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N−K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q−K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q−K frozen bits are allocated to the N−K frozen bit-channels and the q additional frozen bit-channels.

    Abstract translation: 一种用于增加编码可靠性的方法包括生成包括标准极性码部分和附加冻结部分的扩展极性码的发生器矩阵。 标准极码部分具有N位通道，包括K个信息位通道和N-K个冻结位通道。 额外的冻结部分有q个额外的冻结位通道。 在K个信息位通道中，q个信息位通道使用q个额外的冻结位通道进行重新极化。 该方法还包括接收包括K个信息比特和N + q-K个冻结比特的输入向量，并且使用生成矩阵将输入向量变换为包括N + q个编码比特的输出向量。 K个信息比特分配给K个信息比特信道，并且N + q-K个冻结比特被分配给N-K个冻结比特信道和q个附加冻结比特信道。

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