公开(公告)号：US20200119025A1

公开(公告)日：2020-04-16

申请号：US16159753

申请日：2018-10-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Wei JIANG ,  Chieh-Fang CHEN ,  Jia-Rong CHIOU

IPC: H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582 ,  G11C16/04 ,  G11C5/06 ,  G11C5/02 ,  G11C5/12 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8234

Abstract: A 3D memory device includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a memory layer and a channel layer. The insulating layers are alternately stacked with the conductive layers on the substrate to form a multi-layers stacking structure, wherein the multi-layers stacking structure has at least one trench penetrating through the insulating layers and the conductive layers. The memory layer covers on the multi-layers stacking structure and at least extends onto a sidewall of the trench. The cannel layer covers on the memory layer and includes an upper portion adjacent to an opening of the trench, a lower portion adjacent to a bottom of the trench and a string portion disposed on the sidewall, wherein the string portion connects the upper portion with the lower portion and has a doping concentration substantially lower than that of the upper portion and lower portion.

公开(公告)号：US20200335510A1

公开(公告)日：2020-10-22

申请号：US16387650

申请日：2019-04-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Wei JIANG ,  Kuo-Pin CHANG ,  Chieh-Fang CHEN

IPC: H01L27/1158 ,  H01L29/417 ,  H01L21/762

Abstract: A semiconductor structure includes a substrate, conductive layers, dielectric layers, an isolation structure, a first memory structure, and a second memory structure. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The isolation structure is disposed on the substrate and through the conductive layers and the dielectric layers. Each of the first and second memory structures has a radius of curvature. The first and second memory structures penetrate through the conductive layers and the dielectric layers and are disposed on opposite sidewalls of the isolation structure. Each of the first and second memory structures includes protecting structures and a memory structure layer including a memory storage layer. The protecting structures are disposed at two ends of the memory storage layer, and an etching selectivity to the protecting structures is different from an etching selectivity to the memory storage layer.