公开(公告)号：US20200119025A1

公开(公告)日：2020-04-16

申请号：US16159753

申请日：2018-10-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Wei JIANG ,  Chieh-Fang CHEN ,  Jia-Rong CHIOU

IPC: H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582 ,  G11C16/04 ,  G11C5/06 ,  G11C5/02 ,  G11C5/12 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8234

Abstract: A 3D memory device includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a memory layer and a channel layer. The insulating layers are alternately stacked with the conductive layers on the substrate to form a multi-layers stacking structure, wherein the multi-layers stacking structure has at least one trench penetrating through the insulating layers and the conductive layers. The memory layer covers on the multi-layers stacking structure and at least extends onto a sidewall of the trench. The cannel layer covers on the memory layer and includes an upper portion adjacent to an opening of the trench, a lower portion adjacent to a bottom of the trench and a string portion disposed on the sidewall, wherein the string portion connects the upper portion with the lower portion and has a doping concentration substantially lower than that of the upper portion and lower portion.

公开(公告)号：US20210118900A1

公开(公告)日：2021-04-22

申请号：US16658262

申请日：2019-10-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Wei JIANG ,  Jia-Rong CHIOU

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11568

Abstract: A memory device includes a channel element, a memory element, and an electrode element. The channel element includes a first channel portion, a second channel portion, and a middle channel portion between the first channel portion and the second channel portion. The first channel portion has a first sidewall channel surface and a second sidewall channel surface opposing to the first sidewall channel surface. The middle channel portion has a third sidewall channel surface and a fourth sidewall channel surface opposing to the third sidewall channel surface. The first sidewall channel surface and the second sidewall channel surface of the first channel portion are outside the third sidewall channel surface and the fourth sidewall channel surface of the middle channel portion respectively. A memory cell is defined in the memory element between the channel element and the electrode element.

公开(公告)号：US20200091163A1

公开(公告)日：2020-03-19

申请号：US16132539

申请日：2018-09-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Wei JIANG ,  Jia-Rong CHIOU

IPC: H01L27/11556 ,  H01L27/11524

Abstract: A memory device and a manufacturing method for the same are provided. The memory device comprises a NAND memory string. The NAND memory string includes a U-shape channel, a first inversion gate electrode and a second inversion gate electrode. The U-shape channel includes a bottom channel surface, a first outer channel sidewall and a second outer channel sidewall. The bottom channel surface is between the first outer channel sidewall and the second outer channel sidewall opposing to the first outer channel sidewall. The first inversion gate electrode is electrically coupled to the U-shape channel and is disposed under bottom channel surface. The second inversion gate electrode is electrically coupled to the U-shape channel and is disposed outside the first outer channel sidewall, and separated from the first inversion gate electrode.

公开(公告)号：US20210143170A1

公开(公告)日：2021-05-13

申请号：US16680626

申请日：2019-11-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Wei JIANG ,  Chih-Wei HU ,  Jia-Rong CHIOU

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A memory device and a method for manufacturing the same are provided. A memory device includes a drain pillar structure, a source pillar structure, a charge trapping structure, a vertical channel structure and a gate structure. The drain pillar structure is formed in a first opening. The source pillar structure is formed in a second opening. The vertical channel structure and the vertical channel structure are formed in a hole partially overlapping the first opening and the second opening. The vertical channel structure is divided into two arc channel parts by the drain pillar structure and the source pillar structure. The gate structure surrounds the drain pillar structure, the source pillar structure and the vertical channel structure.

公开(公告)号：US20210126006A1

公开(公告)日：2021-04-29

申请号：US16661040

申请日：2019-10-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Wei JIANG ,  Jia-Rong CHIOU

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/45 ,  H01L29/417 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306 ,  H01L29/423

Abstract: A memory device includes a channel element, a memory element, and an electrode element. The channel element has an open ring shape. A memory cell is defined in the memory element between the channel element and the electrode element.