LOW TEMPERATURE TRANSITION METAL OXIDE FOR MEMORY DEVICE
    1.
    发明申请
    LOW TEMPERATURE TRANSITION METAL OXIDE FOR MEMORY DEVICE 有权
    用于存储器件的低温过渡金属氧化物

    公开(公告)号:US20140264232A1

    公开(公告)日:2014-09-18

    申请号:US13895059

    申请日:2013-05-15

    Abstract: A metal oxide formed by in situ oxidation assisted by radiation induced photo-acid is described. The method includes depositing a photosensitive material over a metal surface of an electrode. Upon exposure to radiation (for example ultraviolet light), a component, such as a photo-acid generator, of the photosensitive material forms an oxidizing reactant, such as a photo acid, which causes oxidation of the metal at the metal surface. As a result of the oxidation, a layer of metal oxide is formed. The photosensitive material can then be removed, and subsequent elements of the component can be formed in contact with the metal oxide layer. The metal oxide can be a transition metal oxide by oxidation of a transition metal. The metal oxide layer can be applied as a memory element in a programmable resistance memory cell. The metal oxide can be an element of a programmable metallization cell.

    Abstract translation: 描述了由辐射诱导的光酸辅助形成的原位氧化物形成的金属氧化物。 该方法包括将感光材料沉积在电极的金属表面上。 感光材料暴露于辐射(例如紫外光)时,诸如光酸产生剂的组分形成氧化反应物,例如导致金属在金属表面氧化的光酸。 作为氧化的结果,形成金属氧化物层。 然后可以去除感光材料,并且可以将元件的后续元件形成为与金属氧化物层接触。 金属氧化物可以通过过渡金属的氧化而成为过渡金属氧化物。 金属氧化物层可以作为可编程电阻存储单元中的存储元件来应用。 金属氧化物可以是可编程金属化电池的元件。

    3D MEMORY PROCESS AND STRUCTURES
    2.
    发明申请
    3D MEMORY PROCESS AND STRUCTURES 有权
    3D记忆过程和结构

    公开(公告)号:US20140264615A1

    公开(公告)日:2014-09-18

    申请号:US13914539

    申请日:2013-06-10

    Abstract: A semiconductor device includes a substrate, a stack structure and a transistor. The substrate includes a first region and a second region. The stack structure is formed over the substrate in the first region. The transistor structure has a gate formed in the second region. A bottom portion of the gate structure is disposed at a height from the substrate that is less than a height between the substrate and a bottom portion of the stack structure.

    Abstract translation: 半导体器件包括衬底,堆叠结构和晶体管。 衬底包括第一区域和第二区域。 堆叠结构形成在第一区域中的衬底上。 晶体管结构具有形成在第二区域中的栅极。 栅极结构的底部设置在距离衬底的高度处,该高度小于衬底和堆叠结构的底部之间的高度。

    3D SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    3.
    发明申请
    3D SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    3D半导体结构及其制造方法

    公开(公告)号:US20140264524A1

    公开(公告)日:2014-09-18

    申请号:US13868918

    申请日:2013-04-23

    Inventor: ERH-KUN LAI

    CPC classification number: H01L21/28282 H01L21/764 H01L27/11578

    Abstract: A semiconductor structure includes a plurality of stacked strips on a substrate and a plurality of conductive lines on the stacked strips. The stacked strips and the conductive lines are arranged orthogonally to each other and a conductive liner is formed there between. A first air gap fills the space between the two adjacent stacked strips and under one of the conductive lines, which is positioned on top of said two adjacent stacked strips, whereas a second air gap is between the two adjacent conductive lines. The material of the conductive liner is different from that of the conductive lines. The distance between the two adjacent stacked strips is below 200 nm, and the aspect ratio of the stacked strip is at least 1.

    Abstract translation: 半导体结构包括在衬底上的多个堆叠条带和堆叠条带上的多个导电线。 堆叠的条带和导线彼此正交布置,并且在其间形成导电衬垫。 第一气隙填充两个相邻堆叠条带之间的空间,以及位于所述两个相邻堆叠条带顶部的导电线之一下方,而第二气隙位于两条相邻导电线之间。 导电衬垫的材料与导电线的材料不同。 两个相邻堆叠条带之间的距离低于200nm,堆叠条带的纵横比至少为1。

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