公开(公告)号：US20210057002A1

公开(公告)日：2021-02-25

申请号：US16850788

申请日：2020-04-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chia-Jung CHEN ,  Chin-Hung CHANG ,  Ken-Hui CHEN

IPC: G11C7/10 ,  G11C7/12 ,  H04L9/06 ,  H04L9/32 ,  H04L29/06

Abstract: A memory device, including a secure command decoder implementing security logic configured to detect commands carrying an encrypted immediate data payload from a requesting host, authenticate the host as source of the command, decode the immediate data and perform a memory access command called for by a command portion of the decrypted immediate data upon the storage cells of the memory device using the non-command portion of the decrypted immediate data, as well as to encrypt any result from executing the command portion prior to returning the result to the requesting host, and an input/output interface for I/O data units supporting multiple hosts.

公开(公告)号：US20190189222A1

公开(公告)日：2019-06-20

申请号：US15841598

申请日：2017-12-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long CHANG ,  Ken-Hui CHEN ,  Shang-Chi YANG

IPC: G11C16/26 ,  G11C16/04 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4093 ,  G06F13/40 ,  G06F13/16 ,  G06F3/06 ,  G06F12/02

Abstract: A memory device is disclosed in the present invention, comprising a memory array, a logic circuit, a sense amplifier circuit and a read buffer. The logic circuit is configured to perform a read operation in response to a read command and a start address. During the read operation, the logic circuit finds a target data in the memory array. The sense amplifier circuit is configured to read the target data from the memory array during the read operation. The read buffer is configured to temporarily stores and outputs the target data during the read operation. When an interruption event occurs during the read operation, the read buffer preserves a buffer content of the read buffer, and the logic circuit records a read status.

公开(公告)号：US20250014617A1

公开(公告)日：2025-01-09

申请号：US18888661

申请日：2024-09-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung CHANG ,  Chia-Jung CHEN ,  Ken-Hui CHEN ,  Kuen-Long CHANG

IPC: G11C7/24 ,  G06F21/44 ,  H04L9/32

Abstract: A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

公开(公告)号：US20160232950A1

公开(公告)日：2016-08-11

申请号：US14619810

申请日：2015-02-11

Applicant: Macronix International Co., Ltd.

Inventor： Kuen-Long CHANG ,  Ken-Hui CHEN ,  Ming-Chih HSIEH

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G06F12/0246 ,  G11C7/1015 ,  G11C7/1045 ,  G11C16/06

Abstract: A memory device includes a memory array and a logic unit communicatively coupled to the memory array. The memory array includes a plurality of pages for storing array data and a plurality of extra arrays respectively corresponding to the plurality of pages for storing extra data. The logic unit is configured to receive a read instruction, and perform a read operation in a first access mode or in a second access mode. In the first access mode, the logic unit sequentially reads out the array data stored in the plurality of pages. In the second access mode, the logic unit sequentially reads out the array data stored in the plurality of pages and the extra data stored in the plurality of extra arrays.

Abstract translation: 存储器件包括存储器阵列和通信地耦合到存储器阵列的逻辑单元。 存储器阵列包括用于存储阵列数据的多个页面和分别对应于用于存储额外数据的多个页面的多个额外阵列。 逻辑单元被配置为接收读取指令，并且以第一访问模式或第二访问模式执行读取操作。 在第一访问模式中，逻辑单元顺序地读出存储在多个页面中的阵列数据。 在第二访问模式下，逻辑单元顺序地读出存储在多个页面中的阵列数据和存储在多个额外阵列中的额外数据。

公开(公告)号：US20160204772A1

公开(公告)日：2016-07-14

申请号：US14860761

申请日：2015-09-22

Applicant: Macronix International Co., Ltd.

Inventor： Kuan-Ming LU ,  Chun-Hsiung HUNG ,  Chun-Yi LEE ,  Ken-Hui CHEN ,  Kuen-Long CHANG

IPC: H03K5/1534

CPC classification number: H03K5/1534

Abstract: A power drop detector circuit includes a detect element, for coupling to a first source voltage, for detecting a voltage level of the first source voltage, and a memory element coupled to the detect element and switchable between a first memory state and a second memory state based on the voltage level of the first source voltage.

Abstract translation: 功率损失检测器电路包括检测元件，用于耦合到第一源极电压，用于检测第一源电压的电压电平;以及存储器元件，耦合到检测元件，并且可在第一存储器状态和第二存储器状态之间切换 基于第一源电压的电压电平。

公开(公告)号：US20240274170A1

公开(公告)日：2024-08-15

申请号：US18109455

申请日：2023-02-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung HUNG ,  Ken-Hui CHEN ,  Shang-Chi YANG ,  Tung-Yu LI

IPC: G11C7/12 ,  G06F7/544 ,  G11C8/08

CPC classification number: G11C7/12 ,  G06F7/5443 ,  G11C8/08

Abstract: Compute-in-memory CIM operations using signed bits produce signed outputs. A circuit for CIM operations comprises an array of memory cells arranged in columns and rows, memory cells in columns connected to corresponding bit lines, and memory cells in rows connected to corresponding word lines. The array is programmable to store signed weights in sets of memory cells, the sets being operatively coupled with a corresponding pair of bit lines and a corresponding pair of word lines. Word line drivers are configured to drive true and complement voltages representing signed inputs on respective word lines in selected pairs of word lines. Sensing circuits are configured to sense differences between first and second currents on respective bit lines in selected pairs of bit lines and to produce signed outputs for the selected pairs of bit lines as a function of the difference.

公开(公告)号：US20230386541A1

公开(公告)日：2023-11-30

申请号：US18231611

申请日：2023-08-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung CHANG ,  Chia-Jung CHEN ,  Ken-Hui CHEN ,  Kuen-Long CHANG

IPC: G11C7/24 ,  H04L9/32 ,  G06F21/44

CPC classification number: G11C7/24 ,  H04L9/3278 ,  G06F21/44

Abstract: A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

公开(公告)号：US20230315340A1

公开(公告)日：2023-10-05

申请号：US17824226

申请日：2022-05-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chia-Jung CHEN ,  Chin-Hung CHANG ,  Ken-Hui CHEN

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0622 ,  G06F3/0679

Abstract: A memory device includes a command decoder that implements security logic to detect a command sequence to read a security region of a memory array with continuous encrypted data and to output/input specific contexts for the data. Output/input of specific contexts can be during a dummy cycle to achieve greater performance. A host interfacing can, for example, execute a single command to both get the encrypted data and specific contexts that were used to encrypt the data. Our technology can implement transferring data on the system bus in ciphertext and encrypted by a different Nonce or a different session key than used in a previous transfer operation. In this way, data will be represented with different ciphertext on the bus at different sessions; thereby defending against a replay attack.

公开(公告)号：US20220139434A1

公开(公告)日：2022-05-05

申请号：US17087085

申请日：2020-11-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung CHANG ,  Chia-Jung CHEN ,  Ken-Hui CHEN ,  Kuen-Long CHANG

IPC: G11C7/24 ,  G06F21/44 ,  H04L9/32

Abstract: A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

公开(公告)号：US20200371861A1

公开(公告)日：2020-11-26

申请号：US16419430

申请日：2019-05-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ken-Hui CHEN ,  Kuen-Long CHANG ,  Yi-Fan CHANG

IPC: G06F11/10 ,  G06F3/06

Abstract: An integrated circuit device can comprise addressable memory, and a receiver. Data integrity logic can be coupled to the input data path and configured to receive a data stream having a reference address, and a plurality of data chunks with data integrity codes. Also, the data integrity logic can include a configuration store to store configuration data for the data integrity checking. Also, the integrated circuit can include logic to parse the data chunks and the data integrity codes from the data stream, and logic to compute computed data integrity codes of data chunks in the received data stream, and compare the computed data integrity codes with received data integrity codes to test for data errors in the received data stream. The data integrity logic includes logic responsive to the configuration data that control the data integrity logic. In one aspect, the data integrity data indicates a floating boundary data integrity mode or a fixed boundary data integrity mode.