公开(公告)号：US20220013180A1

公开(公告)日：2022-01-13

申请号：US17105669

申请日：2020-11-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Tzu-Hsuan HSU ,  Po-Kai HSU ,  Teng-Hao YEH ,  Hang-Ting LUE

IPC: G11C16/26 ,  G11C16/14

Abstract: Provided is an operation method for a memory device, the operation method comprising: performing an erase operation; performing a verify-read operation on a memory cell to generate a cell current, the memory cell including a first transistor and a second transistor; checking whether the cell current is lower than a first cell current threshold; when the cell current is not lower than the first cell current threshold, increasing a memory gate voltage until the cell current is lower than the first cell current threshold, wherein the memory gate voltage is applied to the first transistor; fixing the memory gate voltage and increasing a drain voltage; checking whether the cell current is lower than a second cell current threshold; and if the cell current is not lower than the second cell current threshold, increasing the drain voltage until the cell current is lower than the second cell current threshold.