公开(公告)号：US11049572B1

公开(公告)日：2021-06-29

申请号：US16811896

申请日：2020-03-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Chung-Kuang Chen ,  Yi-Ting Lai

IPC: G11C16/26 ,  G11C7/12 ,  G11C16/24

Abstract: A memory device, a source line voltage adjuster and a source line voltage adjusting method thereof are provided. The source line voltage adjuster includes an operation amplifier, a current drainer and a current generator. The operation amplifier includes a first input end coupled to a common source line and a second input end for receiving a reference voltage. The operation amplifier generates an bias voltage. The current drainer drains a drain current from the common source line according to the bias voltage. The current generator provides an output current for the common source line. The current generator generates a first current according to the bias voltage, and generates a second current according to a reference current. The current generator generates the output current according to a difference of the second current and the first current.

公开(公告)号：US09508446B1

公开(公告)日：2016-11-29

申请号：US14749460

申请日：2015-06-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chung-Kuang Chen ,  Yi-Ting Lai

IPC: G11C16/04 ,  G11C16/28 ,  G11C7/04 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/063

Abstract: One aspect of the technology is a memory device comprising a memory array, a sense circuit, and temperature compensated bias circuitry. The memory array is electrically coupled between a bit line bias circuit and a common source line. The bit line bias circuit generates a temperature compensated sense current through the memory array. The temperature compensated bias circuitry controls the bit line bias circuit to generate the temperature compensated sense current through the memory array.

Abstract translation: 该技术的一个方面是包括存储器阵列，感测电路和温度补偿偏置电路的存储器件。 存储器阵列电耦合在位线偏置电路和公共源极线之间。 位线偏置电路通过存储器阵列产生温度补偿的感测电流。 温度补偿偏置电路控制位线偏置电路，以产生通过存储器阵列的温度补偿检测电流。

公开(公告)号：US10599583B2

公开(公告)日：2020-03-24

申请号：US16105230

申请日：2018-08-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Ting Lai ,  Chih-He Chiang

IPC: G06F9/34 ,  G06F12/02 ,  G06F12/00 ,  G06F12/1009 ,  G06F12/10 ,  G06F12/06 ,  G06F12/0802

Abstract: A pre-match method includes: receiving an initial address; gradually increasing a current address according to the initial address; adding an offset value to the current address for generating a match address; generating a hit parameter by comparing the match address with at least one defect address stored in the mapping table; generating a redundancy address corresponding to the match address; and setting a Y-direction address as either the redundancy address or the current address according to the hit parameter.