公开(公告)号：US12094554B2

公开(公告)日：2024-09-17

申请号：US17960149

申请日：2022-10-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Chung-Han Wu ,  Che-Wei Liang ,  Chih-He Chiang ,  Shang-Chi Yang

IPC: G11C29/52 ,  G05F3/26

CPC classification number: G11C29/52 ,  G05F3/262

Abstract: A memory device, a failure bits detector, and a failure bits detection method thereof are provided. The failure bits detector includes a current generator, a current mirror, and a comparator. The current generator generates a first current according to a reference code. The current mirror mirrors the first current to generate a second current at a second end of the current mirror. The comparator compares a first voltage at a first input end with a second voltage at a second input end to generate a detection result.

公开(公告)号：US10304540B1

公开(公告)日：2019-05-28

申请号：US15841688

申请日：2017-12-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-He Chiang ,  Yi-Ching Liu

IPC: G11C16/04 ,  G11C16/12 ,  G11C11/4074 ,  G11C11/4096 ,  G11C7/06 ,  G06F13/40 ,  G11C7/12

CPC classification number: G11C16/12 ,  G06F13/4004 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/4096 ,  G11C16/0483

Abstract: A memory device includes a memory array including a number of memory cell strings, a number of bit lines, a number of pre-charge circuits coupled to the memory cell strings, and a number of sense amplifier circuits coupled to the memory cell strings through the bit lines. Each memory cell string includes at least one first select transistor, a second select transistor and at least one memory cell. Each bit line includes a third select transistor, and is coupled to a memory cell string. During a pre-charging stage, the pre-charge circuits provide a first voltage to pre-charge the memory cell strings. During a programming stage, for the memory cell strings to be inhibited, the sense amplifier circuits provide a second voltage lower than the first voltage. For the memory cell strings to be programmed, the sense amplifier circuits provide a third voltage lower than the second voltage.

公开(公告)号：US10599583B2

公开(公告)日：2020-03-24

申请号：US16105230

申请日：2018-08-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Ting Lai ,  Chih-He Chiang

IPC: G06F9/34 ,  G06F12/02 ,  G06F12/00 ,  G06F12/1009 ,  G06F12/10 ,  G06F12/06 ,  G06F12/0802

Abstract: A pre-match method includes: receiving an initial address; gradually increasing a current address according to the initial address; adding an offset value to the current address for generating a match address; generating a hit parameter by comparing the match address with at least one defect address stored in the mapping table; generating a redundancy address corresponding to the match address; and setting a Y-direction address as either the redundancy address or the current address according to the hit parameter.

公开(公告)号：US20240120018A1

公开(公告)日：2024-04-11

申请号：US17960149

申请日：2022-10-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Chung-Han Wu ,  Che-Wei Liang ,  Chih-He Chiang ,  Shang-Chi Yang

IPC: G11C29/52 ,  G05F3/26

CPC classification number: G11C29/52 ,  G05F3/262

Abstract: A memory device, a failure bits detector, and a failure bits detection method thereof are provided. The failure bits detector includes a current generator, a current mirror, and a comparator. The current generator generates a first current according to a reference code. The current mirror mirrors the first current to generate a second current at a second end of the current mirror. The comparator compares a first voltage at a first input end with a second voltage at a second input end to generate a detection result.