公开(公告)号：US10600843B2

公开(公告)日：2020-03-24

申请号：US15428509

申请日：2017-02-09

Applicant: MARVELL INTERNATIONAL LTD.

Inventor： Ralf Richter ,  Yu-Teh Chiang ,  Ran Yan

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16 ,  H01L43/12

Abstract: A memory device structure includes a wafer substrate and a magnetic tunnel junction (MTJ) positioned above an upper surface of the wafer substrate. The MTJ includes a first magnetic layer, a second magnetic layer laterally adjacent the first magnetic layer, and a nonmagnetic layer interposed between the first and second magnetic layers, wherein the first magnetic layer, the nonmagnetic layer and the second magnetic layer comprise a substantially vertical layer stack that extends along a first direction that is substantially perpendicular to the upper surface of the wafer substrate. A first contact is electrically coupled to the first magnetic layer and a second contact is electrically coupled to the second magnetic layer.