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    SYSTEMS AND METHODS FOR PERFORMING PHASE ERROR CORRECTION
    1.
    发明申请
    SYSTEMS AND METHODS FOR PERFORMING PHASE ERROR CORRECTION 审中-公开

    公开(公告)号：US20180091162A1

    公开(公告)日：2018-03-29

    申请号：US15366820

    申请日：2016-12-01

    Applicant: Marvell World Trade Ltd.

    Inventor： Zhao Liu ,  Wen Yan ,  Zhenhua Xiong ,  Liang Yuan ,  Hongzheng Han ,  Yuan Lu

    IPC: H03L7/099 ,  H03L7/091

    Abstract: Systems and methods for performing phase error correction are provided. A reference clock signal and a target clock signal are received. A first value is generated based on a first amount of time between a first edge of the reference clock signal and a corresponding first edge of the target clock signal. A phase of the target clock signal is adjusted a first time based on a given amount computed using the first value. After the phase of the target clock signal is adjusted, a second value is generated based on a second amount of time between a second edge of the reference clock signal and a corresponding second edge of the target clock signal. The phase of the target clock signal is adjusted a second time based on the given amount, the first value, and the second value.

    Systems and methods for performing phase error correction
    3.
    发明授权
    Systems and methods for performing phase error correction 有权

    公开(公告)号：US10897260B2

    公开(公告)日：2021-01-19

    申请号：US15366820

    申请日：2016-12-01

    Applicant: Marvell World Trade Ltd.

    Inventor： Zhao Liu ,  Wen Yan ,  Zhenhua Xiong ,  Liang Yuan ,  Hongzheng Han ,  Yuan Lu

    IPC: H03L7/099 ,  H03L7/183 ,  H03L7/093 ,  H03L7/091

    Abstract: Systems and methods for performing phase error correction are provided. A reference clock signal and a target clock signal are received. A first value is generated based on a first amount of time between a first edge of the reference clock signal and a corresponding first edge of the target clock signal. A phase of the target clock signal is adjusted a first time based on a given amount computed using the first value. After the phase of the target clock signal is adjusted, a second value is generated based on a second amount of time between a second edge of the reference clock signal and a corresponding second edge of the target clock signal. The phase of the target clock signal is adjusted a second time based on the given amount, the first value, and the second value.

    Peak detector for amplifier
    5.
    发明授权
    Peak detector for amplifier 有权

    公开(公告)号：US09632523B2

    公开(公告)日：2017-04-25

    申请号：US14510467

    申请日：2014-10-09

    Applicant: MARVELL WORLD TRADE LTD

    Inventor： Ruiqiang Liu ,  Hongzheng Han ,  Tuo Wu

    IPC: G05F5/00 ,  G01R19/00 ,  H02M3/156

    CPC classification number: G05F5/00 ,  G01R19/00 ,  G01R19/04 ,  H02M3/156

    Abstract: Aspects of the disclosure provide a circuit for peak voltage detection. The circuit includes a diode-based peak detector and a compensation circuit. The diode-based peak detector has a first diode, and is configured to receive a signal for peak voltage detection and generate a first voltage of a stable level indicative of a peak voltage of the signal based on the first diode. The compensation circuit has a second diode. The compensation circuit is configured to receive the first voltage and generate a second voltage of a stable level that is independent of the first diode.

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