公开(公告)号：US20140143744A1

公开(公告)日：2014-05-22

申请号：US13683743

申请日：2012-11-21

Applicant: MAXELER TECHNOLOGIES LTD.

Inventor： Robert Gwilym DIMOND

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F7/32 ,  G06F7/38 ,  G06F9/382 ,  G06F9/4403 ,  G06F9/445 ,  G06F9/44505 ,  G06F9/455 ,  G06F17/505 ,  G06F17/5077

Abstract: A method of configuring a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph includes a data path to be implemented in hardware as part of the stream processor, an input, an output, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The data path is partitioned into a plurality of discrete regions, each region operating on a different clock phase and having discrete control logic elements. Phase transition registers to align data separated by a boundary between regions having different clock phases are introduced into the data path at the boundary. The graph and control logic elements define a hardware design for the pipelined parallel stream processor.

Abstract translation: 配置流水线并行流处理器的硬件设计的方法包括获取表示时域中的处理操作的调度图，作为时钟周期的函数。 该图包括要在硬件中实现的数据路径，作为流处理器的一部分，输入，输出和并行分支，以使数据值能够作为增加时钟周期的函数从输入流输出到输出。 数据路径被划分成多个离散区域，每个区域在不同的时钟相位上操作并具有离散的控制逻辑元件。 用于对齐由具有不同时钟相位的区域之间的边界分隔的数据的相移寄存器被引入边界的数据路径。 图形和控制逻辑元素定义流水线并行流处理器的硬件设计。