公开(公告)号：US20240281382A1

公开(公告)日：2024-08-22

申请号：US18235365

申请日：2023-08-18

Applicant: MEDIATEK INC.

Inventor： En-Shou Tang ,  Yuan-Chun Lin ,  Kai-Hsiang Chang ,  Yi-Che Tsai

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F13/16

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F13/1689

Abstract: A memory processing system includes a processor, a main memory, and a MMU coupled to the processor and the main memory. The processor is used to generate a plurality of virtual addresses. The main memory includes a plurality of data corresponding to physical addresses in a main page table. The main page table is used to map the plurality of virtual addresses to the plurality of physical addresses. The memory management unit includes a TLB coupled to the processor and the main memory, a table walk unit coupled to the TLB and the main memory, and a merger coupled to the TLB and the processor. The TLB performs address translation by retrieving a physical address according to a virtual address from a first page table in the TLB or a second page table in the table walk unit or the main page table in the main memory.