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公开(公告)号：US20180323953A1
公开(公告)日：2018-11-08
申请号：US15927077
申请日：2018-03-20
Applicant: MEDIATEK INC.
Inventor： Li-Hung Chiueh , Tse-Hsien Yeh , Chen-Yu Hsiao
IPC: H04L7/00
CPC classification number: H04L7/0041 , H04L7/0079 , H04L7/0091
Abstract: The present invention provides a receiver, wherein the receiver includes a plurality of receiving circuit and a skew detection and alignment circuit. The receiving circuit is arranged for receiving a plurality of input signals from a plurality of channels, wherein each of the receiving circuits receives at least one of the input signals to generate an output signal. The skew detection and alignment circuit is arranged for determining skew information according to at least one of the input signals and the output signals, wherein the skew information is used to control delay amounts corresponding to the input signals or the output signals.
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公开(公告)号：US20190045090A1
公开(公告)日：2019-02-07
申请号：US16027263
申请日：2018-07-03
Applicant: MEDIATEK INC.
Inventor： Li-Hung Chiueh , Man-Ju Lee , Chen-Yu Hsiao
Abstract: A reconfigurable pin-to-pin interface includes lane circuits and a reconfiguration circuit. A first lane circuit of the lane circuits obtains a first received signal by receiving a first input signal transmitted via a first lane. A second lane circuit of the lane circuits obtains a second received signal by receiving a second input signal transmitted via a second lane. When the second lane is used as one data lane and the first lane is used as one clock lane, the reconfiguration circuit redirects the first received signal to the second lane circuit for acting as an clock input of the second lane circuit. When the first lane is used as one data lane, the reconfiguration circuit blocks the first received signal from being redirected to the second lane circuit for acting as the clock input of the second lane circuit.
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公开(公告)号：US10284361B2
公开(公告)日：2019-05-07
申请号：US15927077
申请日：2018-03-20
Applicant: MEDIATEK INC.
Inventor： Li-Hung Chiueh , Tse-Hsien Yeh , Chen-Yu Hsiao
IPC: H04L7/00
Abstract: The present invention provides a receiver, wherein the receiver includes a plurality of receiving circuit and a skew detection and alignment circuit. The receiving circuit is arranged for receiving a plurality of input signals from a plurality of channels, wherein each of the receiving circuits receives at least one of the input signals to generate an output signal. The skew detection and alignment circuit is arranged for determining skew information according to at least one of the input signals and the output signals, wherein the skew information is used to control delay amounts corresponding to the input signals or the output signals.
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