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    Clock and data recovery and associated signal processing method
    1.
    发明授权
    Clock and data recovery and associated signal processing method 有权

    公开(公告)号：US11349485B2

    公开(公告)日：2022-05-31

    申请号：US16744188

    申请日：2020-01-16

    Applicant: MEDIATEK INC.

    Inventor： Chien-Kai Kao ,  Tse-Hsien Yeh ,  Shih-Che Hung

    IPC: H03L7/08 ,  H03L7/081 ,  H03L7/087 ,  H04L7/02

    Abstract: The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.

    Clock and data recovery circuit using neural network circuit to obtain frequency difference information
    2.
    发明授权
    Clock and data recovery circuit using neural network circuit to obtain frequency difference information 有权

    公开(公告)号：US12224756B2

    公开(公告)日：2025-02-11

    申请号：US18103472

    申请日：2023-01-30

    Applicant: MEDIATEK INC.

    Inventor： Chien-Kai Kao ,  Shih-Che Hung ,  Tse-Hsien Yeh

    IPC: H04L7/00 ,  G06N3/063 ,  H03L7/08 ,  H03L7/093

    Abstract: The present invention includes a CDR circuit including a phase detector, a neural network circuit, a controller and a clock signal generator is disclosed. The phase detector is configured to use a clock signal to sample an input signal to generate a plurality of phase detection results. The neural network circuit is coupled to the phase detector, and is configured to receive the plurality of phase detection results to determine information of a frequency difference between the clock signal and the input signal. The controller is configured to generate a control signal according to the information of the frequency difference between the clock signal and the input signal. The clock signal generator is configured to use the control signal to adjust a phase or frequency of the clock signal outputted to the phase detector.

    CLOCK AND DATA RECOVERY CIRCUIT USING NEURAL NETWORK CIRCUIT TO OBTAIN FREQUENCY DIFFERENCE INFORMATION
    3.
    发明公开
    CLOCK AND DATA RECOVERY CIRCUIT USING NEURAL NETWORK CIRCUIT TO OBTAIN FREQUENCY DIFFERENCE INFORMATION 审中-公开

    公开(公告)号：US20240007110A1

    公开(公告)日：2024-01-04

    申请号：US18103472

    申请日：2023-01-30

    Applicant: MEDIATEK INC.

    Inventor： Chien-Kai Kao ,  Shih-Che Hung ,  Tse-Hsien Yeh

    IPC: H03L7/08 ,  H03L7/093 ,  G06N3/063

    CPC classification number: H03L7/0807 ,  G06N3/063 ,  H03L7/093

    Abstract: The present invention includes a CDR circuit including a phase detector, a neural network circuit, a controller and a clock signal generator is disclosed. The phase detector is configured to use a clock signal to sample an input signal to generate a plurality of phase detection results. The neural network circuit is coupled to the phase detector, and is configured to receive the plurality of phase detection results to determine information of a frequency difference between the clock signal and the input signal. The controller is configured to generate a control signal according to the information of the frequency difference between the clock signal and the input signal. The clock signal generator is configured to use the control signal to adjust a phase or frequency of the clock signal outputted to the phase detector.

    CHANNEL SKEW CALIBRATION METHOD AND ASSOCIATED RECEIVER AND SYSTEM
    4.
    发明申请
    CHANNEL SKEW CALIBRATION METHOD AND ASSOCIATED RECEIVER AND SYSTEM 审中-公开

    公开(公告)号：US20180323953A1

    公开(公告)日：2018-11-08

    申请号：US15927077

    申请日：2018-03-20

    Applicant: MEDIATEK INC.

    Inventor： Li-Hung Chiueh ,  Tse-Hsien Yeh ,  Chen-Yu Hsiao

    IPC: H04L7/00

    CPC classification number: H04L7/0041 ,  H04L7/0079 ,  H04L7/0091

    Abstract: The present invention provides a receiver, wherein the receiver includes a plurality of receiving circuit and a skew detection and alignment circuit. The receiving circuit is arranged for receiving a plurality of input signals from a plurality of channels, wherein each of the receiving circuits receives at least one of the input signals to generate an output signal. The skew detection and alignment circuit is arranged for determining skew information according to at least one of the input signals and the output signals, wherein the skew information is used to control delay amounts corresponding to the input signals or the output signals.

    CLOCK AND DATA RECOVERY AND ASSOCIATED SIGNAL PROCESSING METHOD
    6.
    发明申请
    CLOCK AND DATA RECOVERY AND ASSOCIATED SIGNAL PROCESSING METHOD 审中-公开

    公开(公告)号：US20200244272A1

    公开(公告)日：2020-07-30

    申请号：US16744188

    申请日：2020-01-16

    Applicant: MEDIATEK INC.

    Inventor： Chien-Kai Kao ,  Tse-Hsien Yeh ,  Shih-Che Hung

    IPC: H03L7/08 ,  H03L7/087 ,  H03L7/081 ,  H04L7/02

    Abstract: The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.

    Channel skew calibration method and associated receiver and system
    7.
    发明授权
    Channel skew calibration method and associated receiver and system 有权

    公开(公告)号：US10284361B2

    公开(公告)日：2019-05-07

    申请号：US15927077

    申请日：2018-03-20

    Applicant: MEDIATEK INC.

    Inventor： Li-Hung Chiueh ,  Tse-Hsien Yeh ,  Chen-Yu Hsiao

    IPC: H04L7/00

    Abstract: The present invention provides a receiver, wherein the receiver includes a plurality of receiving circuit and a skew detection and alignment circuit. The receiving circuit is arranged for receiving a plurality of input signals from a plurality of channels, wherein each of the receiving circuits receives at least one of the input signals to generate an output signal. The skew detection and alignment circuit is arranged for determining skew information according to at least one of the input signals and the output signals, wherein the skew information is used to control delay amounts corresponding to the input signals or the output signals.

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