公开(公告)号：US20160182005A1

公开(公告)日：2016-06-23

申请号：US14736653

申请日：2015-06-11

Applicant: MediaTek Inc.

Inventor： Tao-Yi LEE ,  Po-Sen TSENG ,  Ming-Da TSAI

IPC: H03H7/00 ,  H01F38/14 ,  H03H3/00 ,  H03H7/42 ,  H01F27/28

CPC classification number: H01F27/2847 ,  H01L23/48 ,  H01L23/5222 ,  H01L23/5227

Abstract: A hybrid passive device for synergizing at least one passive component which resides in at least one technology is provided. The hybrid passive device includes a first passive component and a second passive component. The first passive component resides in a first technology of the at least one technology and/or a second technology of the at least one technology, the second technology is different from the first technology, and a technology boundary is arranged between the second technology and the first technology. The second passive component of the at least one passive component is different from the first passive component. The second passive component resides in the first technology and/or the second technology, and the first passive component and the second passive component are electromagnetically coupled to each other through the technology boundary.

Abstract translation: 提供了一种用于协同至少一个无源组件的混合无源器件，其驻留在至少一种技术中。 混合无源器件包括第一无源部件和第二无源部件。 第一无源部件驻留在至少一种技术的第一技术和/或第二技术的第一技术中，第二技术不同于第一技术，并且技术边界被布置在第二技术和第二技术之间 第一技术。 所述至少一个无源部件的所述第二无源部件与所述第一无源部件不同。 第二无源部件位于第一技术和/或第二技术中，并且第一无源部件和第二无源部件通过技术边界彼此电磁耦合。

公开(公告)号：US20210004042A1

公开(公告)日：2021-01-07

申请号：US16918601

申请日：2020-07-01

Applicant: MEDIATEK INC.

Inventor： Chien-Wei TSENG ,  Mohammed Fathey Abdelfattah HASSAN ,  Li-Shin LAI ,  Tzu-Yu YEH ,  Ming-Da TSAI ,  Bernard Mark TENBROEK

IPC: G06F1/12 ,  H03K3/037 ,  G06F1/10

Abstract: Aspects of the disclosure provide methods and apparatuses for generating an internal reset signal that is synchronous to a clock signal. In some embodiments, an apparatus includes a clock switch circuit and a plurality of serially coupled D flip-flops (DFFs). The clock switch circuit receiving the clock signal can output the clock signal in an on state and block the clock signal in an off state. The plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal. If an external reset signal is enabled, the plurality of serially coupled DFFs can enable the internal reset signal. If the external reset signal is disabled, after a predefined number of clock signal cycles, the plurality of serially coupled DFFs can disable the internal reset signal.