公开(公告)号：US20180046577A1

公开(公告)日：2018-02-15

申请号：US15485241

申请日：2017-04-12

Applicant: National Taiwan University ,  MEDIATEK INC.

Inventor： Li-Jhan Chen ,  Po-Han Wang ,  Chia-Lin Yang

IPC: G06F12/0846 ,  G06F9/50 ,  G06F12/084

CPC classification number: G06F12/0848 ,  G06F9/5016 ,  G06F9/5061 ,  G06F12/0842 ,  G06F2212/1016 ,  G06F2212/60 ,  G06F2212/62

Abstract: A thread block managing method, applied to an electronic apparatus comprising a memory and a cache, comprising: (a) transforming memory addresses for the memory to cache addresses of the cache; (b) mapping a memory access range for a thread block to the cache addresses to generate a block access range; (c) calculating block locality between the thread blocks according to the block access range; and (d) allocating the thread blocks to a plurality of multi-processors depending on the block locality.

公开(公告)号：US20180046474A1

公开(公告)日：2018-02-15

申请号：US15677039

申请日：2017-08-15

Applicant: National Taiwan University ,  MEDIATEK INC.

Inventor： Po-Han Wang ,  Chia-Lin Yang

IPC: G06F9/445

CPC classification number: G06F9/44521 ,  G06F9/4843

Abstract: A method for executing a plurality of child kernels invoked on a device side is provided. The child kernels are invoked in response to a parent kernel launched from a host side. The method includes the following steps: linking the child kernels to enqueue a plurality of threads of the child kernels; regrouping the threads of the child kernels to generate a plurality of thread blocks each having N threads, wherein N is a positive integer greater than one; merging the thread blocks to generate a consolidated kernel; and executing the consolidated kernel on the device side to execute a kernel function of the child kernels.

公开(公告)号：US09836396B2

公开(公告)日：2017-12-05

申请号：US14936960

申请日：2015-11-10

Applicant: MediaTek Inc. ,  National Taiwan University

Inventor： Po-Han Wang ,  Cheng-Hsuan Li ,  Chia-Lin Yang

IPC: G06F12/0811 ,  G06F3/06 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0895 ,  G06F12/0864

CPC classification number: G06F12/0811 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0653 ,  G06F3/0673 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/0895 ,  G06F2212/1024 ,  G06F2212/601

Abstract: A last-level cache controller includes a system state monitor and a cache partitioning module. The system state monitor is configured to obtain a latency sensitivity factor, off-chip latency factors, and cache miss information for each of the processor cores. The cache partitioning module is configured to: obtain a first weighted latency according to the latency sensitivity factor, the off-chip latency factors and a first entry of the cache miss information that corresponds to a first cache partition configuration for each of the processor cores; obtain a first aggregated weighted latency according to the first weighted latency of each of the processor cores; determine whether a partition criterion is satisfied, where the partition criterion takes the first aggregated weighted latency into consideration; and partition the cache ways of the last-level cache using the first partition configuration when determining that the partition criterion is satisfied.

公开(公告)号：US20240370379A1

公开(公告)日：2024-11-07

申请号：US18143623

申请日：2023-05-05

Applicant: MEDIATEK INC.

Inventor： Chun-Ming Su ,  Chih-Wei Hung ,  Yi-Lun Lin ,  Kun-Lung Chen ,  Po-Han Wang ,  Ming-Hung Hsieh ,  Yun-Ching Li

IPC: G06F12/126 ,  G06F12/1009

Abstract: An electronic device includes a memory usage identification circuit and a system-level cache (SLC). The memory usage identification circuit obtains a memory usage indicator that depends on memory usage of a storage space allocated in a system memory at which memory access is requested by a physical address. The SLC includes a cache memory and a cache controller. The cache controller performs cache management upon the cache memory according to the physical address and the memory usage indicator.