公开(公告)号：US12081214B2

公开(公告)日：2024-09-03

申请号：US18054032

申请日：2022-11-09

Applicant: MEDIATEK INC.

Inventor： Kin-Hooi Dia ,  Ssu-Yen Wu ,  Shih-Yun Lin

IPC: H03K19/00

CPC classification number: H03K19/0016

Abstract: A clock gating cell is provided. The clock gating cell includes an input stage and an output stage. The input stage receives a first clock signal and at least one input enable signal and generates a first enable signal corresponding to one of the least one input enable signal according to the first clock signal. The output stage is coupled to the input stage. The output stage receives the first enable signal and the first clock signal and generates a clock gating signal according to the first enable signal and the first clock signal. The input stage operates based on a first voltage threshold, and the output stage operates based on a second voltage threshold. The first voltage threshold is different from the second voltage threshold.