公开(公告)号：US12081214B2

公开(公告)日：2024-09-03

申请号：US18054032

申请日：2022-11-09

Applicant: MEDIATEK INC.

Inventor： Kin-Hooi Dia ,  Ssu-Yen Wu ,  Shih-Yun Lin

IPC: H03K19/00

CPC classification number: H03K19/0016

Abstract: A clock gating cell is provided. The clock gating cell includes an input stage and an output stage. The input stage receives a first clock signal and at least one input enable signal and generates a first enable signal corresponding to one of the least one input enable signal according to the first clock signal. The output stage is coupled to the input stage. The output stage receives the first enable signal and the first clock signal and generates a clock gating signal according to the first enable signal and the first clock signal. The input stage operates based on a first voltage threshold, and the output stage operates based on a second voltage threshold. The first voltage threshold is different from the second voltage threshold.

公开(公告)号：US20250005256A1

公开(公告)日：2025-01-02

申请号：US18732655

申请日：2024-06-04

Applicant: MEDIATEK INC.

Inventor： Ho-Chieh Hsieh ,  Kin-Hooi Dia

IPC: G06F30/398 ,  G06F30/392 ,  G06F119/06

Abstract: The present invention provides a method for placing and routing a circuit design on an integrated circuit. The method includes the steps of: placing a plurality of standard cells in the circuit design; searching for the standard cells with power-to-power abutment in the circuit design; and performing an operation on the standard cells with the power-to-power abutment for a power/performance/area optimization.

公开(公告)号：US10361190B2

公开(公告)日：2019-07-23

申请号：US15168507

申请日：2016-05-31

Applicant: MediaTek Inc.

Inventor： Kin-Hooi Dia ,  Hugh Thomas Mair ,  Shao-Hua Huang ,  Wen-Yi Lin

IPC: H03K19/017 ,  H01L27/06 ,  H03K19/003

Abstract: A standard cell circuit includes a standard cell unit and a first resistive device. The standard cell unit is coupled to at least one resistor. The first resistive device is coupled to the standard cell unit and provides a first current path for a first current to flow through.

公开(公告)号：US11714125B2

公开(公告)日：2023-08-01

申请号：US17225101

申请日：2021-04-07

Applicant: MEDIATEK INC.

Inventor： Kin-Hooi Dia ,  Yi-Horng Chiou

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185 ,  H03K3/012 ,  H03K3/037

CPC classification number: G01R31/31721 ,  G01R31/3177 ,  G01R31/318541 ,  H03K3/012 ,  H03K3/037

Abstract: A multi-bit flip-flop (MBFF) has flip-flops connected to form an internal scan chain. One of the flip-flops outputs a first data-out signal at a first data output terminal of the MBFF, and includes a selection circuit, a latch-based circuit, and a data-out stage circuit. The selection circuit transmits a data signal or a test signal to an output node of the selection circuit to serve as an input signal. The latch-based circuit generates a first signal according to the input signal. The data-out stage circuit receives the first signal, and generates the data-out signal according to the first signal. When the MBFF operates in a test mode, the selection circuit transmits the test signal to serve as the input signal, and the data-out stage circuit keeps the data-out signal at a fixed voltage level regardless of a voltage level of the test signal.

公开(公告)号：US20230179187A1

公开(公告)日：2023-06-08

申请号：US17989654

申请日：2022-11-17

Applicant: MEDIATEK INC.

Inventor： Yi-Horng Chiou ,  Kin-Hooi Dia

IPC: H03K3/037

CPC classification number: H03K3/0372

Abstract: A semiconductor device includes a plurality of cell rows, a first functional block and a second functional block. The plurality of cell rows at least includes a first cell row and a second cell row. The first functional block is formed in the first cell row and configured to provide a first predetermined function. The second functional block is formed in the second cell row and configured to provide a second predetermined function which is the same as the first predetermined function. The first cell row and the second cell row have at least one different physical property.

公开(公告)号：US12191310B2

公开(公告)日：2025-01-07

申请号：US17535760

申请日：2021-11-26

Applicant: MEDIATEK INC.

Inventor： Kin-Hooi Dia ,  Ho-Chieh Hsieh

IPC: H01L27/118

Abstract: A semiconductor structure is provided. A logic cell with a logic function includes a plurality of first transistors in an active region over a semiconductor substrate, a second transistor in the active region, a third transistor in the active region, and first and second isolation structures on opposite edges of the active region and extending along the first direction. Each first transistor includes a first gate electrode extending along the first direction. The second transistor includes a second gate electrode extending along the first direction. The third transistor includes a third gate electrode extending along the first direction. The first gate electrodes are disposed between the first and second isolation structures. The second gate electrode is disposed between the first gate electrodes and the first isolation structure. The third gate electrode is disposed between the first gate electrodes and the second isolation structure.

公开(公告)号：US20210359667A1

公开(公告)日：2021-11-18

申请号：US17225101

申请日：2021-04-07

Applicant: MEDIATEK INC.

Inventor： Kin-Hooi Dia ,  Yi-Horng Chiou

IPC: H03K3/012 ,  H03K3/037 ,  G01R31/3177 ,  G01R31/317

Abstract: A multi-bit flip-flop (MBFF) has flip-flops connected to form an internal scan chain. One of the flip-flops outputs a first data-out signal at a first data output terminal of the MBFF, and includes a selection circuit, a latch-based circuit, and a data-out stage circuit. The selection circuit transmits a data signal or a test signal to an output node of the selection circuit to serve as an input signal. The latch-based circuit generates a first signal according to the input signal. The data-out stage circuit receives the first signal, and generates the data-out signal according to the first signal. When the MBFF operates in a test mode, the selection circuit transmits the test signal to serve as the input signal, and the data-out stage circuit keeps the data-out signal at a fixed voltage level regardless of a voltage level of the test signal.