公开(公告)号：US12081214B2

公开(公告)日：2024-09-03

申请号：US18054032

申请日：2022-11-09

申请人： MEDIATEK INC.

发明人： Kin-Hooi Dia ,  Ssu-Yen Wu ,  Shih-Yun Lin

IPC分类号： H03K19/00

CPC分类号： H03K19/0016

摘要： A clock gating cell is provided. The clock gating cell includes an input stage and an output stage. The input stage receives a first clock signal and at least one input enable signal and generates a first enable signal corresponding to one of the least one input enable signal according to the first clock signal. The output stage is coupled to the input stage. The output stage receives the first enable signal and the first clock signal and generates a clock gating signal according to the first enable signal and the first clock signal. The input stage operates based on a first voltage threshold, and the output stage operates based on a second voltage threshold. The first voltage threshold is different from the second voltage threshold.

公开(公告)号：US20220366116A1

公开(公告)日：2022-11-17

申请号：US17673755

申请日：2022-02-16

申请人： MEDIATEK INC.

发明人： Yu-Tung Chang ,  Yi-Chun Tsai ,  Tung-Kai Tsai ,  Yi-Te Chiu ,  Shih-Yun Lin ,  Hung-Ming Chu ,  Yi-Feng Chen

IPC分类号： G06F30/392

摘要： An integrated circuit (IC) may include a plurality of functional blocks, and each functional block of the plurality of functional blocks may include hardware circuits, wherein the plurality of functional blocks may include a first functional block. In addition, the first functional block may include a first macro circuit that is positioned within a first sub-region of the first functional block, wherein among multiple sides of the first sub-region, a first side of the first sub-region is closest to a boundary of the first functional block. Additionally, a first intermediate sub-region of the first functional block is positioned between the first side of the first sub-region and the boundary of the first functional block, and there is no tap cell in the first intermediate sub-region of the first functional block.