公开(公告)号：US20160380624A1

公开(公告)日：2016-12-29

申请号：US15138654

申请日：2016-04-26

Applicant: MediaTek Inc.

Inventor： Ying-Chun WEI ,  Jen-Hang YANG

IPC: H03K5/134 ,  G06F17/50

CPC classification number: H03K5/134 ,  G06F17/505 ,  G06F2217/84 ,  H03K2005/00195

Abstract: A delay cell for generating a desired delay exceeding a minimum delay defined in a standard cell library is provided, which includes a delay element and an output inverter. The delay element receives an input signal to generate an internal signal with a propagation delay relative to the input signal, which includes a P-type transistor, a first resistor, a second resistor, and an N-type transistor. The P-type transistor applies a supply voltage to the first resistor by the input signal. The first resistor is coupled between the P-type transistor and the output inverter. The second resistor is coupled to the output inverter and coupled to the ground through the N-type transistor by the input signal. The output inverter receives the internal signal to generate an output signal with the desired delay, which is dominated by the propagation delay, relative to the input signal.

Abstract translation: 提供了一种用于产生超过在标准单元库中定义的最小延迟的期望延迟的延迟单元，其包括延迟元件和输出反相器。 延迟元件接收输入信号以产生相对于输入信号的传播延迟的内部信号，该输入信号包括P型晶体管，第一电阻器，第二电阻器和N型晶体管。 P型晶体管通过输入信号向第一电阻施加电源电压。 第一个电阻耦合在P型晶体管和输出反相器之间。 第二电阻器耦合到输出反相器，并通过输入信号通过N型晶体管耦合到地。 输出反相器接收内部信号，以相对于输入信号产生具有由传播延迟支配的期望延迟的输出信号。

公开(公告)号：US20200065065A1

公开(公告)日：2020-02-27

申请号：US16111277

申请日：2018-08-24

Applicant: MEDIATEK INC.

Inventor： Ying-Chun WEI ,  Min-Hang HSIEH ,  Jen-Hang YANG

IPC: G06F7/503 ,  H03K19/017

Abstract: A full adder circuit includes a carry out generating circuit and a sum bit generating circuit. The carry out generating circuit is configured to generate a first output signal based on a first input signal, a second input signal and a third input signal. The sum bit generating circuit is configured to receive the first output signal and generate a second output signal based on the first input signal, the second input signal, the third input signal and the first output signal. The first output signal and the second output signal provide results of an arithmetic operation on the first input signal, the second input signal and the third input signal. The sum bit generating circuit includes a first pull-up network and a first pull-down network. There are at most two stacked transistors in at one or both of the first pull-up network and the first pull-down network.

公开(公告)号：US20240369605A1

公开(公告)日：2024-11-07

申请号：US18423531

申请日：2024-01-26

Applicant: MEDIATEK INC.

Inventor： Jen-Hang YANG ,  Ying-Chun WEI

IPC: G01R21/133 ,  G01R15/14

Abstract: A power level detection circuit is provided. The power level detection circuit includes a resistive circuit, a pull-up circuit, a pull-down circuit, and an output terminal. The resistive circuit is coupled between a first power terminal and a first node. The first terminal is coupled to a first supply voltage. The pull-up circuit is coupled between a second power terminal and a second node. The second power terminal is coupled to a second supply voltage. The pull-down circuit is coupled between the second node and a common ground. The output terminal is coupled to the second node and configured to output a detection signal. The pull-up circuit and the pull-down circuit are configured to control a time point that the detection signal starts to transition from a first level to a second level according to the first supply voltage and the second supply voltage.