公开(公告)号：US20180375500A1

公开(公告)日：2018-12-27

申请号：US15634007

申请日：2017-06-27

Applicant: MEDIATEK INC.

Inventor： Min-Hang HSIEH ,  Wei-Min HSU ,  Jen-Hang YANG

IPC: H03K3/356 ,  G01R31/3177 ,  G01R31/317

CPC classification number: H03K3/356104 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3177 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/35625

Abstract: A scan output flip-flop is provided. The scan output flip-flop outputs a scan-out signal at a first output terminal and includes a selection circuit, a control circuit, and a scan-out stage circuit. The selection circuit is controlled by a first test enable signal to transmit a data signal on a first input terminal or a test signal on a second input terminal to an output terminal of the selection circuit to serve as an input signal. The control circuit is coupled to the output terminal of the selection circuit and controlled by a first clock signal to generate a first control signal and a second control signal according to the input signal. The second control signal is the inverse of the first control signal. The scan-out stage circuit is controlled by the first control signal and the second control signal to generate the scan-out signal.

公开(公告)号：US20200065065A1

公开(公告)日：2020-02-27

申请号：US16111277

申请日：2018-08-24

Applicant: MEDIATEK INC.

Inventor： Ying-Chun WEI ,  Min-Hang HSIEH ,  Jen-Hang YANG

IPC: G06F7/503 ,  H03K19/017

Abstract: A full adder circuit includes a carry out generating circuit and a sum bit generating circuit. The carry out generating circuit is configured to generate a first output signal based on a first input signal, a second input signal and a third input signal. The sum bit generating circuit is configured to receive the first output signal and generate a second output signal based on the first input signal, the second input signal, the third input signal and the first output signal. The first output signal and the second output signal provide results of an arithmetic operation on the first input signal, the second input signal and the third input signal. The sum bit generating circuit includes a first pull-up network and a first pull-down network. There are at most two stacked transistors in at one or both of the first pull-up network and the first pull-down network.