公开(公告)号：US20170365594A1

公开(公告)日：2017-12-21

申请号：US15697715

申请日：2017-09-07

Applicant: MediaTek Inc.

Inventor： Jen-Hang YANG

IPC: H01L27/02 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L27/11807 ,  H01L2027/11874

Abstract: An integrated circuit is provided. In one implementation, the integrated circuit includes a first standard cell, comprising at least one first PMOS transistor disposed in a first row in a semiconductor substrate and at least one first NMOS transistor disposed in a first area of a second row in the semiconductor substrate, and a second standard cell, comprising a plurality of second PMOS transistors disposed in the first row and a third row in the semiconductor substrate and a plurality of second NMOS transistors disposed in a second area of the second row in the semiconductor substrate, wherein the second row is adjacent to the first and third rows and arranged between the first and third rows.

公开(公告)号：US20250141446A1

公开(公告)日：2025-05-01

申请号：US19009332

申请日：2025-01-03

Applicant: MEDIATEK INC.

Inventor： Hao-Hsiang YU ,  Jen-Hang YANG

IPC: H03K17/687 ,  H03K19/01 ,  H03K19/20 ,  H10D84/85

Abstract: A buffer circuit is provided to output an output signal at an output node. The buffer circuit includes first and second inverters and first and second switches. The first inverter inverts an input signal. The second inverter is coupled between the first inverter and the output node. The first switch is coupled between a first voltage source terminal and the output node. The second switch is coupled between the output node and a second voltage source terminal. First and second voltages are respectively provided to the first and second voltage source terminals. In response to the input signal switching to a first level from a second level, the first switch is turned on to pre-charge the output node. In response to the input signal transiting to the second level from the first level, the second switch is turned on to pre-discharge the output node.

公开(公告)号：US20250080115A1

公开(公告)日：2025-03-06

申请号：US18952224

申请日：2024-11-19

Applicant: MEDIATEK INC.

Inventor： Bo-Ren LUNG ,  Jen-Hang YANG

IPC: H03K19/00 ,  H03K19/0185

Abstract: An integrated circuit device includes a plurality of selecting modules, wherein each of the plurality of selecting modules is configured to receive a first input signal, a second input signal, a first selecting signal and a second selecting signal, and select the first input signal or the second input signal to generate an output signal according to a first selecting signal and a second selecting signal; and a selecting signal providing module, configured to provide the first selecting signal and the second selecting signal.

公开(公告)号：US20160380624A1

公开(公告)日：2016-12-29

申请号：US15138654

申请日：2016-04-26

Applicant: MediaTek Inc.

Inventor： Ying-Chun WEI ,  Jen-Hang YANG

IPC: H03K5/134 ,  G06F17/50

CPC classification number: H03K5/134 ,  G06F17/505 ,  G06F2217/84 ,  H03K2005/00195

Abstract: A delay cell for generating a desired delay exceeding a minimum delay defined in a standard cell library is provided, which includes a delay element and an output inverter. The delay element receives an input signal to generate an internal signal with a propagation delay relative to the input signal, which includes a P-type transistor, a first resistor, a second resistor, and an N-type transistor. The P-type transistor applies a supply voltage to the first resistor by the input signal. The first resistor is coupled between the P-type transistor and the output inverter. The second resistor is coupled to the output inverter and coupled to the ground through the N-type transistor by the input signal. The output inverter receives the internal signal to generate an output signal with the desired delay, which is dominated by the propagation delay, relative to the input signal.

Abstract translation: 提供了一种用于产生超过在标准单元库中定义的最小延迟的期望延迟的延迟单元，其包括延迟元件和输出反相器。 延迟元件接收输入信号以产生相对于输入信号的传播延迟的内部信号，该输入信号包括P型晶体管，第一电阻器，第二电阻器和N型晶体管。 P型晶体管通过输入信号向第一电阻施加电源电压。 第一个电阻耦合在P型晶体管和输出反相器之间。 第二电阻器耦合到输出反相器，并通过输入信号通过N型晶体管耦合到地。 输出反相器接收内部信号，以相对于输入信号产生具有由传播延迟支配的期望延迟的输出信号。

公开(公告)号：US20240145389A1

公开(公告)日：2024-05-02

申请号：US18361116

申请日：2023-07-28

Applicant: MEDIATEK INC.

Inventor： Li-Chiu WENG ,  Yew Teck TIEO ,  Ming-Hsuan WANG ,  Chia-Cheng CHEN ,  Wei-Yi CHANG ,  Jen-Hang YANG ,  Chien-Hsiung HSU

IPC: H01L23/528

CPC classification number: H01L23/5286

Abstract: A semiconductor chip includes a first intellectual property block. There are a second intellectual property block and a third intellectual property block around the first intellectual property block. There is a multiple metal layer stack over the first intellectual property block, the second intellectual property block, and the third intellectual property block. An interconnect structure is situated in the upper portion of the multiple metal layer stack. The interconnect structure is configured for connecting the first intellectual property block and the second intellectual property block. In addition, at least a part of the interconnect structure extends across and over the third intellectual property block.

公开(公告)号：US20180375500A1

公开(公告)日：2018-12-27

申请号：US15634007

申请日：2017-06-27

Applicant: MEDIATEK INC.

Inventor： Min-Hang HSIEH ,  Wei-Min HSU ,  Jen-Hang YANG

IPC: H03K3/356 ,  G01R31/3177 ,  G01R31/317

CPC classification number: H03K3/356104 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3177 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/35625

Abstract: A scan output flip-flop is provided. The scan output flip-flop outputs a scan-out signal at a first output terminal and includes a selection circuit, a control circuit, and a scan-out stage circuit. The selection circuit is controlled by a first test enable signal to transmit a data signal on a first input terminal or a test signal on a second input terminal to an output terminal of the selection circuit to serve as an input signal. The control circuit is coupled to the output terminal of the selection circuit and controlled by a first clock signal to generate a first control signal and a second control signal according to the input signal. The second control signal is the inverse of the first control signal. The scan-out stage circuit is controlled by the first control signal and the second control signal to generate the scan-out signal.

公开(公告)号：US20150123730A1

公开(公告)日：2015-05-07

申请号：US14297965

申请日：2014-06-06

Applicant: MediaTek Inc.

Inventor： Jen-Hang YANG

IPC: H01L27/02 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L27/11807 ,  H01L2027/11874

Abstract: An integrated circuit is provided. A standard cell includes a plurality of PMOS transistors and a plurality of NMOS transistors. The PMOS transistors are disposed in a first row and a second row in the semiconductor substrate. The NMOS transistors are disposed in a third row in the semiconductor substrate. The third row is adjacent to the first and second rows and arranged between the first and second rows.

Abstract translation: 提供集成电路。 标准单元包括多个PMOS晶体管和多个NMOS晶体管。 PMOS晶体管设置在半导体衬底中的第一行和第二行中。 NMOS晶体管设置在半导体衬底中的第三行中。 第三行与第一行和第二行相邻并且布置在第一行和第二行之间。

公开(公告)号：US20240369605A1

公开(公告)日：2024-11-07

申请号：US18423531

申请日：2024-01-26

Applicant: MEDIATEK INC.

Inventor： Jen-Hang YANG ,  Ying-Chun WEI

IPC: G01R21/133 ,  G01R15/14

Abstract: A power level detection circuit is provided. The power level detection circuit includes a resistive circuit, a pull-up circuit, a pull-down circuit, and an output terminal. The resistive circuit is coupled between a first power terminal and a first node. The first terminal is coupled to a first supply voltage. The pull-up circuit is coupled between a second power terminal and a second node. The second power terminal is coupled to a second supply voltage. The pull-down circuit is coupled between the second node and a common ground. The output terminal is coupled to the second node and configured to output a detection signal. The pull-up circuit and the pull-down circuit are configured to control a time point that the detection signal starts to transition from a first level to a second level according to the first supply voltage and the second supply voltage.

公开(公告)号：US20230308099A1

公开(公告)日：2023-09-28

申请号：US18183359

申请日：2023-03-14

Applicant: MEDIATEK INC.

Inventor： Hao-Hsiang YU ,  Jen-Hang YANG

IPC: H03K17/687 ,  H03K19/20 ,  H01L27/092

CPC classification number: H03K17/6872 ,  H03K19/20 ,  H01L27/0928

Abstract: A buffer circuit is provided to output an output signal at an output node. The buffer circuit includes first and second inverters and first and second switches. The first inverter inverts an input signal. The second inverter is coupled between the first inverter and the output node. The first switch is coupled between a first voltage source terminal and the output node. The second switch is coupled between the output node and a second voltage source terminal. First and second voltages are respectively provided to the first and second voltage source terminals. In response to the input signal switching to a first level from a second level, the first switch is turned on to pre-charge the output node. In response to the input signal transiting to the second level from the first level, the second switch is turned on to pre-discharge the output node.

公开(公告)号：US20230170881A1

公开(公告)日：2023-06-01

申请号：US18049725

申请日：2022-10-26

Applicant: MEDIATEK INC.

Inventor： Wei-Min HSU ,  Jen-Hang YANG

IPC: H03K3/012 ,  H03K19/0185 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/0372 ,  H03K19/018521 ,  H03K19/20

Abstract: A register with data retention includes a master-slave flip-flop, a balloon latch, and a level shifter. The master-slave flip-flop is supplied by a first power voltage. The balloon latch is supplied by a second power voltage. The second power voltage is independent of the first power voltage. The level shifter provides a voltage conversion between the master-slave flip-flop and the balloon latch. A data is stored in the master-slave flip-flop. When the first power voltage is disabled, the balloon latch is configured to temporarily retain the data.