HIGH LINEARITY MIXER USING A 33% DUTY CYCLE CLOCK FOR UNWANTED HARMONIC SUPPRESSION
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    发明申请
    HIGH LINEARITY MIXER USING A 33% DUTY CYCLE CLOCK FOR UNWANTED HARMONIC SUPPRESSION 有权
    使用33%占空比时钟的高线性混频器进行无阻碍的谐波抑制

    公开(公告)号:US20130257508A1

    公开(公告)日:2013-10-03

    申请号:US13653305

    申请日:2012-10-16

    IPC分类号: H03B1/04

    摘要: A mixer circuit is disclosed. The mixer circuit comprises a plurality of mixer elements, wherein there are non-overlapping clock signals provided to the plurality of mixer elements which have a duty cycle of 33 ⅓ percent. Outputs signals of the mixer elements do not contain third order harmonic content of the non-overlapping clock signals. The third-order harmonic of the mixer is eliminated by using mixer which uses voltage sampling on non-overlapping clocks and thereby achieves high linearity. The mixer circuit is further expanded to remove the 1-0 image and even order harmonics.

    摘要翻译: 公开了一种混频器电路。 混频器电路包括多个混频器元件,其中提供给具有33 1/3%占空比的多个混频器元件的非重叠时钟信号。 混频器元件的输出信号不包含非重叠时钟信号的三阶谐波含量。 通过使用在非重叠时钟上采用电压采样的混频器来消除混频器的三阶谐波,从而实现高线性度。 混频器电路进一步扩展以去除1-0图像,甚至排序谐波。