公开(公告)号：US20230110285A1

公开(公告)日：2023-04-13

申请号：US17500598

申请日：2021-10-13

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ilan Pardo ,  Benjamin Fuhrer ,  Noam Korem ,  Gal Yefet ,  Tomer Bar-On

IPC: G06N3/04

Abstract: Apparatuses, systems, and techniques to improve processing efficiency are provided. In at least one embodiment, a processing unit is described as including circuitry that receives an input vector and applies an activation function to the input vector by performing a hardware approximation of the activation function in a vector manner. The circuitry also generates an output vector based on the activation function.

公开(公告)号：US20230229732A1

公开(公告)日：2023-07-20

申请号：US17577059

申请日：2022-01-17

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Tomer Bar-On ,  Noam Dor Korem ,  Gal Yefet ,  Benjamin Fuhrer

IPC: G06F17/17 ,  G06F7/544

CPC classification number: G06F17/17 ,  G06F7/544

Abstract: A method for approximating a mathematical function defined over a range includes initially dividing at least part of the range into a set of segments. For at least a subset of the segments, the mathematical function is approximated within each segment by a respective approximation polynomial. A series of one or more segment-merging iterations is performed, a given iteration including: selecting adjacent segments as candidates for merging; approximating the mathematical function by a candidate approximation polynomial, over at least a merged segment formed by merging the adjacent segments; and, if approximation of the mathematical function meets a specified condition, updating the set of segments by (i) replacing the adjacent segments with the merged segment and (ii) replacing the approximation polynomials of the adjacent segments with the candidate approximation polynomial.

公开(公告)号：US20230110316A1

公开(公告)日：2023-04-13

申请号：US17499580

申请日：2021-10-12

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ilan Pardo ,  Benjamin Fuhrer ,  Galina Ryvchin ,  Gal Yefet

IPC: G06F9/30 ,  G06F17/16 ,  G06F7/544

Abstract: Apparatuses, systems, and techniques to improve processing efficiency. In at least one embodiment, a processing unit includes circuitry that reads a vector from memory and multiplies the vector with a scalar value extracted from a scalar field of a vector register. The scalar field may be specified by an immediate field value that is also used to identify an offset used to define a pointer that points to a location in the memory from which to read the vector.