公开(公告)号：US20210044461A1

公开(公告)日：2021-02-11

申请号：US16943615

申请日：2020-07-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Matan Groen ,  Chen Gaist ,  Hananel Faig

IPC: H04L25/03 ,  H04L7/00 ,  H04L7/033

Abstract: A Decision Feedback Equalizer (DFE) for filtering N symbols includes multiple processing blocks and selection logic. Each of the processing blocks includes a respective number N′

公开(公告)号：US11171816B2

公开(公告)日：2021-11-09

申请号：US16943615

申请日：2020-07-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Matan Groen ,  Chen Gaist ,  Hananel Faig

IPC: H04L25/03 ,  H04L7/00 ,  H04L7/033

Abstract: In some disclosed embodiments, a Decision Feedback Equalizer (DFE) processes multiple symbols in parallel using a novel architecture that avoids violating a timing constraint. The DFE comprises Feed-Back (FB) filters that can be configured to equalizing nonlinear phenomena. Using a Look-Up Table (LUT)-based implementation, the FB filters may implement complex nonlinear functions at low hardware complexity, low latency and low power consumption. A LUT-based implementation of the FB filter supports adaptive FB filtering to changing channel conditions by updating LUT content.

公开(公告)号：US11108536B1

公开(公告)日：2021-08-31

申请号：US16819844

申请日：2020-03-16

Applicant: Mellanox Technologies, Ltd.

Inventor： Hananel Faig ,  David (Dima) Rohlin ,  Matan Groen

IPC: H04L7/033

Abstract: A method for implementing an efficient clock recovery for multilane high-speed Serializer/Deserializer (SerDes) system having M interleaved lanes, has a non-recursive architecture.

公开(公告)号：US20200021500A1

公开(公告)日：2020-01-16

申请号：US16032118

申请日：2018-07-11

Applicant: Mellanox Technologies, Ltd.

Inventor： Nir Einati ,  Matan Groen ,  Shay Zaretsky

IPC: H04L12/24 ,  H03K19/0175 ,  G05B19/05 ,  G06F13/12 ,  H04L12/26

Abstract: An apparatus for displaying status information of a network switch, which includes ports and a dedicated test port, includes an interface, one or more display elements, and circuitry. The interface is configured to connect to the network switch through a dedicated test port in the network switch that is separate from the ports. The circuitry is configured to receive from the network switch, via the interface and the dedicated test port, status information of one or more of the ports, and to display the status information using the display elements.