公开(公告)号：US20250110907A1

公开(公告)日：2025-04-03

申请号：US18477162

申请日：2023-09-28

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ariel Shahar ,  Peter Paneah ,  Vladimir Vainer ,  Afek Bernhard

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems and methods herein are for a Non-Transparent Bridges (NTBs) that are scalable and configurable to use equally sized or spaced windows and a common lookup database for remapping writes without completions. The equally sized or spaced windows in the address space are addressable by a starting address and a size to support communication between host machines or endpoints. The common lookup database is to allow selection of one the windows associated with a mapping between address spaces of different domains and is also to accept remapping writes through the at least one NTB to modify the mapping without need for a completion to be returned to a source of the remapping writes.

公开(公告)号：US20250110906A1

公开(公告)日：2025-04-03

申请号：US18476836

申请日：2023-09-28

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ariel Shahar ,  Peter Paneah ,  Vladimir Vainer ,  Afek Bernhard

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems and methods herein are for a Non-Transparent Bridges (NTBs) that are scalable and configurable to use equally sized or spaced windows and a common lookup database for remapping writes without completions. The equally sized or spaced windows in the address space are addressable by a starting address and a size to support communication between host machines or endpoints. The common lookup database is to allow selection of one the windows associated with a mapping between address spaces of different domains and is also to accept remapping writes through the at least one NTB to modify the mapping without need for a completion to be returned to a source of the remapping writes.

公开(公告)号：US11218397B2

公开(公告)日：2022-01-04

申请号：US16258600

申请日：2019-01-27

Applicant: Mellanox Technologies, Ltd.

Inventor： Peter Paneah ,  Yoni Galezer ,  Vladimir Vainer

IPC: G06F13/42 ,  H04L12/26 ,  G06F11/30 ,  G06F11/36 ,  G06F13/40

Abstract: An apparatus includes a processor, a first interface configured to connect to a bus of the apparatus, a second interface configured to communicate over a packet network, and circuitry. The circuitry is configured to, in a first operational mode, exchange data between the processor and one or more remote devices over the packet network, via the second interface, and in a second operational mode, monitor the bus using the first interface, detect a predefined trigger event occurring on the bus and, in response to detecting the trigger event, log one or more transactions on the bus that are adjacent to the trigger event and generate one or more protocol-analysis packets comprising at least part of the logged transactions.

公开(公告)号：US20200244562A1

公开(公告)日：2020-07-30

申请号：US16258600

申请日：2019-01-27

Applicant: Mellanox Technologies, Ltd.

Inventor： Peter Paneah ,  Yoni Galezer ,  Vladimir Vainer

IPC: H04L12/26 ,  G06F11/30 ,  G06F11/36 ,  G06F13/40 ,  G06F13/42

Abstract: An apparatus includes a processor, a first interface configured to connect to a bus of the apparatus, a second interface configured to communicate over a packet network, and circuitry. The circuitry is configured to, in a first operational mode, exchange data between the processor and one or more remote devices over the packet network, via the second interface, and in a second operational mode, monitor the bus using the first interface, detect a predefined trigger event occurring on the bus and, in response to detecting the trigger event, log one or more transactions on the bus that are adjacent to the trigger event and generate one or more protocol-analysis packets comprising at least part of the logged transactions.